Satish C. Chaparala

Mechanical shock testing and modeling of PC motherboards

Due to a variety of manufacturing, environmental, shipping, and end-use conditions, personal computer (PC) motherboards and other circuit boards may be subjected to potentially damaging mechanical shock loads. As these loads can lead to product failure, an understanding of the response of circuit boards subjected to suddenly applied loads is necessary. A first step in this direction is to develop and validate modeling approaches for the simulation of shock load response on PC motherboards. Since building a detailed model of the motherboard would be difficult due to the wide variation in length scales and localized concentrations of mass/stiffness due to components, two simplified modeling approaches were investigated: global property smearing and simple block modeling. Both of these methods approximate the influence of regions with widely differing stiffness and mass properties resulting from the placement of components, connectors and other items on the circuit board while simultaneously avoiding problems associated with developing large, expensive, detailed models. Both the shock response spectrum (SRS) method and an implicit direct integration (i.e., time-marching) scheme were used to simulate the shock response. In addition to modeling, programmed shock pulse and drop table measurements were carried out on the motherboard to validate and understand the limits of the finite element simulations. The results show that the predicted peak response at a number of locations on the motherboard correlated well with measurements made during the shock loading; however, improvements in the simple models are still required to strengthen their correlation. Surprisingly, the simple global smear approach produced good results with significantly less solution time than the block model. Finally, it was found that the SRS method significantly under predicted the response of the motherboard. This may be due to large displacements induced in the motherboard by the high-g shock loads.

Effect of geometry and temperature cycle on the reliability of WLCSP solder joints

The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.

Room Temperature CW Operation of Short Wavelength Quantum Cascade Lasers Made of Strain Balanced Ga

We present our recent development of short wavelength quantum cascade lasers (QCLs) made of strain balanced Ga_xIn_1-xAs/Al_yIn_1-yAs material on InP substrates. We demonstrate room temperature continuous-wave (CW) lasing of the fundamental lateral mode at four wavelengths of 4.6, 4.0, 3.8, and 3.5 μm. We obtained 60-mW CW output power at 10 °C and 3.55-μm wavelength, which is the shortest CW lasing wavelength demonstrated at room temperature by a QCL, to the best of our knowledge. We also performed a life test on λ = 4.6 μm QCL chips. To date, we have accumulated the life test data for more than 11 000 and 4100 h under two aging conditions, 20°C and 0.85-A constant current, and 60°C and 1-A constant current, respectively.

_{\bm x}

Over the past several years, the semiconductor industry has seen some tremendous developments in using glass as an interposer substrate. Glass has many properties that make it an ideal substrate for interposer substrates such as: ultra-high resistivity, low dielectric constant, ultra-low electrical loss and adjustable coefficient of thermal expansion (CTE) that allows management of 3D-IC stacks. Regardless of technical performance, any glass based solution must also provide significant cost advantages in substrate material, via formation, and subsequent processing. Cost-Effective Solutions In this paper, we will cover how fusion formed glass provides cost-effective solutions for the manufacturing of interposer materials for as-formed 100 μm precision substrate with a pristine surface, without the need for polishing, thus eliminating the manufacturing steps for polishing and thinning. Design Considerations For effective implementation of glass substrates, processing costs for through-glass-vias (TGV) on ultra-thin glass is also a challenge. This paper will reference data from several different designs to demonstrate the impact of design on Cornings TGV process cost relative to silicon solutions. It will also highlight processing lessons learned in fabricating TGV interposers from bare glass into complete packaged test vehicles and their impact on cost. Via Capabilities Furthermore, glasses via formation capabilities have dramatically improved over the past several months. Fully populated wafers with >100,000 through and blind holes (25 μm diameter) are fabricated today with 20μm diameters. We report on the significant enhancements demonstrated on important quality parameters. We will also report on strength parameters measured on TGV wafers and positive implications with respect to product reliability.

In

We report the life test results for 9 4.6-µm planar buried heterostructure quantum cascade lasers made of strain-balanced GaInAs/AlInAs/InP materials grown by metal organic vapor-phase epitaxy. No facet coating was deposited, and the devices were mounted on CuW submounts using AuSn solder. The aging condition is continuous wave operation at a heat-sink temperature of 22 o C with a constant current of 0.85A, corresponding to current densities of 4.7 and 2.7 kA/cm 2 , for lasers with widths of 4 and 7 µm, respectively. All lasers survived 5000 h aging, and most devices showed improved performance during the first 1000 h of aging.

_{\bm {1-x}}

— Efficient and compact green lasers are keystone components for micro-projector applications in mobile devices. An architecture that consists of an infrared-producing DBR (distributed Bragg reflector) laser with a frequency-doubling crystal is used to synthesize a green laser that has high electrical-to-optical conversion efficiency and can be modulated at speeds required for scanner-based projectors. The design and performance of a green-laser package that uses adaptive optics to overcome the challenge of maintaining alignment between the waveguides of the DBR laser and the frequency-doubling crystal over temperature and lifetime is described. The adaptive optics technology that is employed uses the piezo-based smooth impact drive mechanism (SIDM) actuators that offer a very small step size and a range of travel adequate for the alignment operation. The laser is shown to be compact (0.7 cm3 in volume) and capable of a wall-plug efficiency approaching 10% (at 100-mW green power). It was demonstrated that the adaptive optics enables operation over a wide temperature range (10–60°C) and provides the capability for low-cost assembly of the device.

As/Al

The Wafer Level-Chip-Scale Package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.

_{\bm y}

The micro-SMD is a Wafer Level-Chip-Scale Package (WL-CSP) designed to have external dimensions equal to that of the silicon device. This new package type extends flip-chip packaging technology to standard surface mount technology. The package has been successfully targeted for low pin count (less than 30), high volume applications such as cellular phones, hand-held PDAs, etc. Since the WL-CSP is typically used without underfill, solder joint reliability is of prime concern. A good understanding of the device failure mechanism when assembled on different board configurations is critical to the development of an accurate predictive model of solder fatigue. This paper presents results of a joint effort to develop a parametric predictive model of the solder joint reliability of the micro-SMD subjected to thermo-mechanical stresses. An 18 I/O micro-SMD was used as the primary test vehicle for the thermal cycling and thermal shock tests performed with different ramp/hold profiles. The parametric model developed can be extended to different pin count and die size of WL-CSPs with eutectic solder.

In

Response of brittle plate to impact loads has been the subject of many research studies [1–7]. Specifically, glass presents a wide variety of applications in daily life, and helps to protect the displays of smartphones, tablets, PCs, and TVs from everyday wear and tear. Therefore, the necessity of glass to resist scratches, drop impacts, and bumps from everyday use leads to the importance of investigation of the glass response under dynamic impact loading. The ball drop test has been applied in the past, specifying an energy threshold as a prediction metric. Use of energy as the key parameter in impact testing is limited, since it does not account for the time spent in contact during the impact event. This study attempts to establish a reliable metric for impact testing based on a momentum change threshold. The deformation and the strain of the glass will be obtained by the Digital Image Correlation (DIC) system, while the rebound velocity will be measured with the high speed cameras. The global and local measurements are conducted to verify the accuracy of the experimental results. Finally, the FEA model is developed using ANSYS/LS-DYNA to provide a comprehensive understanding of the dynamic response of the glass. Excellent correlation in deflection is obtained between the measurements and predictions.Copyright

_{\bm {1-y}}

Green lasers with high efficiency are keystone components for mobile projectors. We demonstrate a miniature device (<0.7 cc volume) that utilizes adaptive optics for operation over a 50 °C temperature range without requiring a thermo-electric cooler. The use of adaptive optics also helps in reducing the cost of the laser assembly.