James M. Pitarresi

Transient Dynamic Simulation and Full-Field Test Validation for A Slim-PCB Of Mobile Phone under Drop / Impact

Product durability due to drop shock is a critical element for assessment of reliability for handheld devices. So far, no simulation model for a board-level drop has been extensively validated by experiments for its predictions of global (full-field) dynamic response. Accelerometers and strain gages which are traditionally utilized to measure the response at selected locations, fail to assess the global strain gradients and complex mode shapes. In this work, a novel non-contact optical technique has been proposed for measurement of full-field impact response. Pair of synchronized high-speed cameras capture the images of board assembly subjected to JEDEC standard impact, at rates up to 15,000 pictures per second. A digital image correlation (DIC) system has been integrated with the cameras to analyze the acquired images to give dynamic deformation, shape and strain over the entire surface of board during impact. A finite element model for the drop test has been developed using ANSYS/LS-DYNA. The numerical solution has been fully validated against experimental measurements of acceleration, strain and warpage at series of instants of time after impact. Effect of tightening torque at PCB mounts has been studied comprehensively with regards to the eigenvalues and mode shapes, and the necessity for accurate modeling of dynamic contact conditions existing at the supports has been demonstrated. Simulation model has been further used to assess the drop impact reliability of components on the board. Excellent correlation of all simulation results with the measured data validates the experimental and numerical propositions made in this work for analyzing a board-level drop impact.

Computationally Efficient Approaches to Characterize the Dynamic Response of Microstructures Under Mechanical Shock

We present computationally efficient models and approaches to simulate the response of microstructures under mechanical shock. These approaches include a Galerkin-based reduced-order model and a hybrid approach utilizing the response of structures to static loads combined with the dynamic shock spectrum of a spring-mass-damper system. To demonstrate the accuracy and efficiency of these approaches, we apply them on cantilever and clamped-clamped microbeams, and compare their predictions with analytical and finite-element (FE) results. We conclude that the hybrid approach is computationally efficient and accurate for microstructures behaving linearly in both quasi-static and dynamic loading conditions. The hybrid approach enables using simple analytical expressions that can be easily utilized by microelectromechanical system designers to judge the reliability of their devices. We show that reduced-order models are capable of capturing accurately the dynamic behavior of microstructures under shock pulses of various amplitudes (low-g and high-g), damping conditions, structural boundaries, and can capture linear and nonlinear behavior. Our results indicate that modeling the shock force as a quasi-static force for microstructures with low-natural frequencies may lead to erroneous results. High-g loading cases are investigated. Significant increase in the computational cost of simulations is reported when using traditional FE models because of the activation of higher order modes. The developed reduced-order model employing at least six modes is shown to be efficient in such cases. Design parameters are investigated to determine their effect on the shock resistance of microstructures. It is concluded that increasing air damping and tensile residual stresses improves the shock resistance of microstructures. A case study for the response of an optical fiber switch to shock is presented.

Mechanical shock testing and modeling of PC motherboards

Due to a variety of manufacturing, environmental, shipping, and end-use conditions, personal computer (PC) motherboards and other circuit boards may be subjected to potentially damaging mechanical shock loads. As these loads can lead to product failure, an understanding of the response of circuit boards subjected to suddenly applied loads is necessary. A first step in this direction is to develop and validate modeling approaches for the simulation of shock load response on PC motherboards. Since building a detailed model of the motherboard would be difficult due to the wide variation in length scales and localized concentrations of mass/stiffness due to components, two simplified modeling approaches were investigated: global property smearing and simple block modeling. Both of these methods approximate the influence of regions with widely differing stiffness and mass properties resulting from the placement of components, connectors and other items on the circuit board while simultaneously avoiding problems associated with developing large, expensive, detailed models. Both the shock response spectrum (SRS) method and an implicit direct integration (i.e., time-marching) scheme were used to simulate the shock response. In addition to modeling, programmed shock pulse and drop table measurements were carried out on the motherboard to validate and understand the limits of the finite element simulations. The results show that the predicted peak response at a number of locations on the motherboard correlated well with measurements made during the shock loading; however, improvements in the simple models are still required to strengthen their correlation. Surprisingly, the simple global smear approach produced good results with significantly less solution time than the block model. Finally, it was found that the SRS method significantly under predicted the response of the motherboard. This may be due to large displacements induced in the motherboard by the high-g shock loads.

Dynamic modeling and measurement of personal computer motherboards

This paper addresses basic modeling issues regarding the mechanical shock and random vibration response of a typical personal computer motherboard. Finite element modeling of an ATX-style motherboard was used to estimate the modal characteristics and dynamic response. Locally stiffened regions, such as sockets and large components, were modeled as simple blocks. The elastic modulus for these regions was determined by performing a 3-point bend tests on samples removed from the motherboard. The mode shapes and natural frequencies of the motherboard were computed and correlated with measurement. The dynamic response, due to random base excitation of the motherboard, was predicted by the model and showed very good correlation with measured acceleration response values. Mechanical shock response analysis was approached using two methods: direct time integration and the shock response spectrum method. Both provided good correlation with the measured peak acceleration response to an applied half-sine shock pulse. In addition, the predicted transient response was well correlated with acceleration time history measurements made during shock loading. It was observed that the shock response was dominated by the fundamental mode of the motherboard. Simple guidelines are presented for modeling of personal computer motherboards subjected to random base excitation and shock loads.

Modeling of printed circuit cards subject to vibration

Some of the current methodologies used in modeling printed circuit cards subjected to vibration are introduced. An overview of experimental and computational methods of determining the natural frequencies and mode shapes of circuit cards populated with various module types is presented. Methodologies for correlating experimentally derived vibration data with the computer models are explored. By using the modal assurance criterion as a correlation measure, it is shown that smearing or homogenizing the material properties is effective in preserving a good degree of correlation in the lower modes of vibration of an example printed circuit card. It is also observed that modeling the entire card as a single composite modeling region is surprisingly effective. However, increasing the number of composite modeling regions to five produced a better overall correlation of the modes of interest.<<ETX>>

Effect of geometry and temperature cycle on the reliability of WLCSP solder joints

The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.

Assessment of PCB pad cratering resistance by joint level testing

Cracking of the laminate under the solder connect pads, known as pad craters, is a reliability issue related to mechanical stresses generated from either mechanical or thermal loading. The current study aims to establish a mechanistic understanding of pad cratering through the use of joint-level testing techniques. Both strength and cyclic loading lifetime are considered, and the results indicate that these two loading modes are not correlated. The individual crack paths within a crater are found to differ with laminate material, glass style (if any), and micro-via details. Various degradation mechanisms are found to have a significant effect on this failure mode with both thermal and moisture exposure showing decreased laminate performance. Finally, the relationship between joint-level testing is compared to the performance in board level drop test. Here we see that joint-level testing is far more general, in terms of qualifying the robustness of the laminate.

Measurement of Transient Dynamic Response of Circuit Boards of a Handheld Device During Drop Using 3D Digital Image Correlation

In this work, a new experimental methodology for analyzing the drop impact response is assessed using a pair of high-speed digital cameras and 3D digital image correlation software. Two different test boards are subjected to Joint Electron Device Engineering Council (JEDEC) standard free-fall impact conditions of half-sine pulse of 1500 G in magnitude and 0.5 ms in duration. The drop is monitored using a pair of synchronized high-speed cameras at a rate of up to 15,000 frames per second. The acquired images are subsequently analyzed to give full-field dynamic deformation, shape, and strain over the entire board during and after impact. To validate this new methodology for analyzing the impact response, the in-plane strain as well as the out-of-plane acceleration at selected locations were measured simultaneously during the drop using strain gauge and accelerometers and were compared with those obtained using high-speed cameras and 3D digital image correlation presented in this paper. Comparison reveals excellent correlation of the transient behavior of the board during impact and confirms the feasibility of using the full-field measurement technique used in this study. DOI: 10.1115/1.3000097

Effect of voids on the reliability of BGA/CSP solder joints

Voids in solder joints have been considered as a defect in electronics assembly. The factors that affect void formation are complex and involve the interaction of many other factors. There are no established standards for void size and void area in a solder joint for it to be deemed defective. Inspection criteria have been very subjective. The effect of voids on the reliability of a BGA/CSP solder joint may depend not only on the size, but also on other factors such as frequency and location. This study focused on investigating the effect of voids on the reliability of solder joints. The effect of void size, location and frequency on reliability were studied. Testing was done by a mechanical deflection testing (torsion) system and air to air thermal cycling (-40/spl deg//125/spl deg/C). Failures were analyzed and failure modes were identified by cross sectional analysis. Additionally, a finite element model was developed for a package with voids of varying sizes in the corner solder joint of the package. The results from the model were compared with the results from reliability testing and are presented in this paper. Analysis indicates that voids reduce the solder joint life. Voids which are greater than 50% of the solder joint area decrease the mechanical robustness of the solder joints. Small voids also have an effect on reliability. However, this effect is dependent on the frequency and location of voids.

Board level energy correlation and interconnect reliability modeling under drop impact

Portable products as well as some larger products may see failures by a high strain rate mechanical loading like that seen in a high or low level drop/shock event. Within the portable product industry there is a wide range of product design, usage and loading conditions. Because of this, standards such as JEDEC, which is meant to generate comparative results addressing component reliability, do little or nothing to generalize the reliability of specific assemblies. To do this we need to consider both failure rates and failure mechanisms to better understand how specific loading conditions affect the failure of an assembly.