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Dive into the research topics where Satish Damaraju is active.

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Featured researches published by Satish Damaraju.


asian solid state circuits conference | 2007

Penryn: 45-nm next generation Intel® core™ 2 processor

Varghese George; Sanjeev Jahagirdar; Chao Tong; Ken Smits; Satish Damaraju; Scott E. Siers; Ves A. Naydenov; Tanveer R. Khondker; Sanjib Sarkar; Puneet Singh

This paper describes Penryn (codename), Intel–s next generation family of processors implemented in a 45nm High-k metal gate silicon process technology and designed to meet a wide range of power envelopes and market segments. It is a dual-core, 64-bit CPU based on the Core™ microarchitecture with a unified 24-way L2 cache of 6MB. Key new features in Penryn include a Fast Radix- 16 Divider, an SSE4 instruction set, a radically new Power Management state (Deep Power Down) and Enhanced Dynamic Acceleration Technology (EDAT). Active and leakage power reduction techniques are used throughout the design to reduce power consumption while not compromising the scalability requirements. The chip is offered in various package technologies including a MCP version for the Quad-core products.


asian solid state circuits conference | 2012

The first 22nm IA multi-CPU and GPU system-on-chip using tri-gate transistors

Scott E. Siers; Satish Damaraju; Varghese George; Sanjeev Jahagirdar; Tanveer R. Khondker; Robert Milstrey; Sanjib Sarkar; Israel Stolero; Arun Subbiah

This paper will go over some of the details of Intels latest Core offering, the first 22nm design code-named Ivy Bridge. In addition to the new process, Ivy Bridge offers several new features including significant improvements to the Graphics and Media block including DX11 support, new power/thermal control optimizations, support for 3 simultaneous displays, new security features and new PCIE Gen3 support. The new 22nm process provides exceptional low voltage performance advantage as well as a 2x improvement in density. The paper also reviews changes to leverage the low operating voltages as well as details of IO, PLL and clocking. Ivy Bridge was introduced into the market on April 23, 2012.


international solid-state circuits conference | 2012

A 22nm IA multi-CPU and GPU System-on-Chip

Satish Damaraju; Varghese George; Sanjeev Jahagirdar; Tanveer R. Khondker; Robert Milstrey; Sanjib Sarkar; Scott E. Siers; Israel Stolero; Arun Subbiah


Archive | 2004

Low power cache architecture

Subramaniam J. Maiyuran; Lyman Moulton; Salvador Palanca; Satish Damaraju


Archive | 2004

Reducing power consumption in a sequential cache

Satish Damaraju; Subramaniam Maiyuran; Peter J. Smith; Navin Monteiro


Archive | 2006

Power-performance modulation in caches using a smart least recently used scheme

Satish Damaraju; Subramaniam Maiyuran; Truyen Trinh; Parag Raval; Peter J. Smith


Archive | 2011

Method, apparatus, and system for energy efficiency and energy conservation including dynamic cache sizing and cache operating voltage management for optimal power performance

Inder M. Sodhi; Satish Damaraju; Sanjeev S. Jahagirdar; Ryan D. Wells


Archive | 2006

Look ahead LRU array update scheme to minimize clobber in sequentially accessed memory

Peter J. Smith; Satish Damaraju; Subramaniam Maiyuran


Archive | 2009

MEMORY ARRAY HAVING EXTENDED WRITE OPERATION

Iqbal Rajwani; Satish Damaraju; Niranjan L. Cooray; Muhammad M. Khellah; Jaydeep P. Kulkarni


Archive | 2006

LOW POWER DELAY CONTROLLED ZERO SENSITIVE SENSE AMPLIFIER

Iqbal Rajwani; Satish Damaraju

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