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Dive into the research topics where Scott E. Siers is active.

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Featured researches published by Scott E. Siers.


asian solid state circuits conference | 2007

Penryn: 45-nm next generation Intel® core™ 2 processor

Varghese George; Sanjeev Jahagirdar; Chao Tong; Ken Smits; Satish Damaraju; Scott E. Siers; Ves A. Naydenov; Tanveer R. Khondker; Sanjib Sarkar; Puneet Singh

This paper describes Penryn (codename), Intel–s next generation family of processors implemented in a 45nm High-k metal gate silicon process technology and designed to meet a wide range of power envelopes and market segments. It is a dual-core, 64-bit CPU based on the Core™ microarchitecture with a unified 24-way L2 cache of 6MB. Key new features in Penryn include a Fast Radix- 16 Divider, an SSE4 instruction set, a radically new Power Management state (Deep Power Down) and Enhanced Dynamic Acceleration Technology (EDAT). Active and leakage power reduction techniques are used throughout the design to reduce power consumption while not compromising the scalability requirements. The chip is offered in various package technologies including a MCP version for the Quad-core products.


asian solid state circuits conference | 2012

The first 22nm IA multi-CPU and GPU system-on-chip using tri-gate transistors

Scott E. Siers; Satish Damaraju; Varghese George; Sanjeev Jahagirdar; Tanveer R. Khondker; Robert Milstrey; Sanjib Sarkar; Israel Stolero; Arun Subbiah

This paper will go over some of the details of Intels latest Core offering, the first 22nm design code-named Ivy Bridge. In addition to the new process, Ivy Bridge offers several new features including significant improvements to the Graphics and Media block including DX11 support, new power/thermal control optimizations, support for 3 simultaneous displays, new security features and new PCIE Gen3 support. The new 22nm process provides exceptional low voltage performance advantage as well as a 2x improvement in density. The paper also reviews changes to leverage the low operating voltages as well as details of IO, PLL and clocking. Ivy Bridge was introduced into the market on April 23, 2012.


international solid-state circuits conference | 2012

A 22nm IA multi-CPU and GPU System-on-Chip

Satish Damaraju; Varghese George; Sanjeev Jahagirdar; Tanveer R. Khondker; Robert Milstrey; Sanjib Sarkar; Scott E. Siers; Israel Stolero; Arun Subbiah


Archive | 2004

DOMINO CIRCUIT TOPOLOGY

Hans L. Yeager; Scott E. Siers; Brian T. Ormson


Archive | 1998

Booth multiplier for handling variable width operands

Mohammad Abdallah; Scott E. Siers


Archive | 2008

Processor power consumption control and voltage drop via micro-architectural bandwidth throttling

Sanjeev Jahagirdar; Edward V. Gamsaragan; Scott E. Siers


Archive | 1998

Fast bi-directional tristateable line driver

Subramaniam Maiyuran; Sanjay Dabral; Thu M. Do; Scott E. Siers; Mehrdad Mohebbi


Archive | 2010

Power reducing logic and non-destructive latch circuits and applications

Hon Shing Lau; Scott E. Siers; Ruchira Liyanage


Archive | 2008

SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A DEVICE USING REGISTER FILES

Satish Damaraju; Scott E. Siers; Omar Malik


Archive | 2011

MEMORY CELL WRITE

Satish Damaraju; Ak R. Ahmed; Scott E. Siers

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