Satomi Ogawa

A switched-capacitor interface for differential capacitance transducers

For high-accuracy signal processing of differential capacitance transducers, an interface circuitry based on a switched-capacitor sample/hold circuit is developed. Driven by nonoverlapping two-phase clocks, the interface produces the output voltage which is proportional to the ratio of difference-to-sum of two capacitors of a differential transducer. SPICE simulations show that 0.1% resolution is easily achievable with the simple configuration. Experimental results are given to confirm the simulation.

A high performance class AB current conveyor

A class AB CMOS current conveyor is developed for wideband current-mode signal processing, It consists of a differential stage for the voltage input, a single-ended push-pull stage for the current input, and current mirrors for the current output. The differential and push-pull stages form a unity-gain buffer, to realize exact voltage-following action and low impedance at the current input node. Simulations based on a 0.6 /spl mu/m CMOS process show that the impedance at the current input node is 3.5 /spl Omega/ and the current and voltage transfer characteristics extend beyond 100 MHz. This performance and the low power consumption are quite satisfactory for most applications.

A switched-capacitor successive-approximation A/D converter

A switched-capacitor successive-approximation analog-to-digital (A/D) converter that incorporates a serial digital-to-analog (D/A) subconverter for generating the threshold voltage sequence is developed. The conversion process is insensitive to parasitic capacitances and offset voltages of the comparator and operational amplifiers. Error analyses and Spice simulations show that a resolution higher than 11 b, a sampling rate up to 440 ksamples/s with 10-b resolution, and a power consumption less than 60 mW are attainable with monolithic implementation using present CMOS technologies. The required chip area is small because of a low device count. The architecture described is therefore best suited for high-accuracy, medium-speed A/D converters in application-specific integrated circuits (ASICs). A prototype converter breadboarded using discrete components has confirmed the principles of operation. >

Clock-feedthrough compensated switched-capacitor circuits

Novel switched-capacitor circuits are presented which greatly suppress the clock-feedthrough effect. The principle is based on the cancellation of feedthrough charges stored in two capacitors. The circuit operations are also insensitive to parasitic capacitances and offset voltages of op-amps, and thus allow an accurate analog signal processing. As a typical example, a cyclic analog-to-digital converter is proposed. Error analyses show that a resolution higher than 12 bits is attainable by implementing the architecture using presently available CMOS technologies. Experimental waveforms are also given to confirm the principles of operation.<<ETX>>

An algorithmic analog-to-digital converter using unity-gain buffers

An algorithmic stage for bipolar 1-b analog-to-digital (A/D) conversion using a unity-gain buffer is proposed. Cyclic and pipeline A/D converter architectures using this stage iteratively or in cascade are also described. Error analysis and SPICE simulations show that a conversion accuracy higher than 8-b and a conversion rate up to 10 Mb/s are attainable with presently available 3- mu m CMOS technologies. Video frequency operation is also possible with finer linewidths. The component requirement is minimum, and thus it is best suited for an analog interface in application-specific integrated circuits (ASIC). A prototype cyclid A/D converter built using discrete components confirms the principles of operation. >

A buffer-based algorithmic analog-to-digital converter

An algorithmic analog-to-digital (A/D) converter is proposed which uses unity-gain buffers instead of op-amps to perform the analog arithmetic operation. Error analysis shows that a conversion accuracy higher than 8 b is possible with presently available CMOS technologies. The device count is minimum, and thus it is suited for an A/D converter implemented by ASICs. A prototype converter built using discrete components has confirmed the principles of operation.<<ETX>>

A switched-capacitor successive-approximation analog-to-digital converter

A successive-approximation analog-to-digital converter is developed using switched-capacitor techniques. The threshold voltage sequence with which the input analog voltage is compared is generated by a 1-b digital-to-analog converter. The conversion process is insensitive to parasitic capacitances and offset voltages of the comparator and op-amps. Error analysis shows that a resolution higher than 11-b is attainable by implementing the architecture using presently available CMOS technologies. The component requirement is minimum. A prototype converter breadboarded using discrete components has confirmed the principles of operation.<<ETX>>

A switched-capacitor interface for high-accuracy, high-speed ratiometric signal processing of differential capacitance transducers

For high-accuracy signal processing of differential capacitance transducers, interface circuitry based on a switched-capacitor sample/hold circuit is developed. Driven by nonoverlapping two-phase clocks, the interface produces an output voltage which is proportional to the ratio of difference-to-sum of two capacitors of a differential transducer. Performances of a prototype chip fabricated using 0.6 /spl mu/m n-well CMOS process were measured and compared with those simulated by HSPICE. The measured results indicate that 0.1% resolution is achievable with the proposed interface and the temperature-dependence of the interface is small. An interface circuit improved for smaller temperature-dependence is also proposed and its operation is confirmed experimentally.