Satoshi Muraoka

Power distribution network design method based on frequency-dependent target impedance for jitter design of memory interface

This paper proposes a PDN design method using frequency-dependent target impedance considering frequency properties of jitter sensitivity of the IO buffer to power supply noise and switching current profile. We confirmed that this design and the resulting jitter of the I/O interface attributable to power supply noise meet the target value of less than 5 %UI.

PCB trace modeling and equalizer design method for 10 Gbps backplane

This paper discusses accurate PCB modeling methods for 10 Gbps differential signal traces. We added two approaches to the conventional modeling method: (1) We simulated the glass cloth and epoxy distribution in the PCB dielectric to simulate common/differential mode conversion noise (SCD21). (2) We applied a frequency-dependent dielectric constant to the electromagnetic analysis model based on a Djordjevic-Sarkar model to introduce a frequency-dependent group delay. Applying these two additional modeling elements, we obtained accurate SCD21 and jitter properties consistent with measurement results. We also demonstrated an equalizer design based on the improved PCB model. By flattening the frequency dependence of the group delay as well as trace losses for the transmission paths, including the equalizer, by adjusting the properties of the peaking amplifier for the equalizer circuit, we reduced jitter by up to 10 ps for 10 Gbps signalling.

Study of the insertion loss of a differential pair of through holes for the 25-Gbps serial interconnect

To design future high-speed interconnects that operate above 25 Gbps, accurate scattering parameters (s-parameters) of structures, such as through holes, are necessary. We estimated the s-parameters of a differential pair of through holes by using the de-embedding technique to eliminate undesirable loss and delay in the feed lines connected to the through holes. By comparing this insertion loss and the estimated insertion loss of a corresponding electromagnetic (EM) simulation model, we found that the distance between the center of the drill holes and the center of their clearance could be a reason for the increase in the insertion loss of the through holes in addition to the open stub effect above 20 GHz. We also discuss the reason for the error in the de-embedding from the viewpoint of measurement repeatability. We estimated contact resistance, parasitic capacitance, and parasitic inductance at the air coplanar (ACP) probe tips from the measured s-parameters. The result shows that these parameters varied about 0.1 Ω, 0.1 nH, and 0.05 pF due to reasons such as the contact condition or the flatness of the PCB. To mitigate these parasitic lumped elements, probes with smaller tips are preferable when we measure the s-parameters of structures for de-embedding.