Satoshi Shimamoto

Metrology of LER: influence of line-edge roughness (LER) on transistor performance

The influence of line-edge roughness (LER) on transistor performance was investigated experimentally and the preciously proposed guideline for CD and LER measurements was examined. First, regarding the transistor-performance measurements, a shift of roll-off curves caused by LER within a gate pattern was observed. Moreover, the effect of transistor-width fluctuation originating from long-period LER was found to cause a variation in transistor performance. Second, regarding LER and CD metrology, the previously reported guideline was validated by using KrF and ArF resist-pattern samples. It was found that both CD and LER should be evaluated with the 2-μm-long inspection area. Based on this guideline, a comprehensive approach for evaluating LER and CD for transistor fabrication process is presented. The authors consider that this procedure can provide useful information for the 65-nm-node technology and beyond.

High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure

High-performance p-channel lateral double-diffused MOS (LDMOS) transistors designed to operate in a wide voltage range from 35 to 200 V and built using silicon-on-insulator LDMOS platform technology were studied. A novel channel structure was applied, and consequently, a high saturation drain current of 172 μA/μm in the 200-V p-channel LDMOS transistor was achieved, which is comparable to that of an n-channel LDMOS transistor. A low on -resistance of 3470 mΩ·mm2 was obtained while maintaining high on- and off-state breakdown voltages of -240 and -284 V. The 35-200-V LDMOS transistors with low on-resistance were also demonstrated by optimizing the layout, i.e., the reduced surface field structure and field plates.

High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology

We have developed high performance Pch-LDMOS transistors in wide range rated voltage from 35V to 200V SOI LDMOS platform technology. By applying a novel channel structure, a high saturation drain current of 172 μA/μm in the 200V Pch-LDMOS transistor was achieved, which is comparable to that of the Nch-LDMOS transistor. A low on-resistance of 3470 mΩ∗ mm2 was obtained while maintaining high on- and off-state breakdown voltages of −240 and −284 V. The 35V to 200V LDMOS transistors with a competitive low on-resistance were also demonstrated by layout optimization such as RESURF structure and field plate.

Atomic Layer Control for Suppressing Extrinsic Defects in Ultrathin SiON Gate Insulator of Advanced Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

By measuring the minimum supply voltage for normal operation of test random access memories, we detected low-density extrinsic defects in silicon-oxynitride (SiON) gate insulators that were formed by state-of-the-art technologies. The density of the detected defects had a strong correlation with optical thickness dopt, which was ellipsometrically measured, regardless of the processing conditions of the SiON films. We propose to maintain the dopt above a threshold value of 1.7 nm to suppress the problems caused by the defects. The optimization of post nitridation annealing (PNA) condition is promising for meeting the criterion without sacrificing device performance. By elaborate investigations based on the Clausius–Mosotti relation, we found that the optical thickness of SiON films is approximately proportional to the atomic area density in the films. On the basis of this finding, we developed a model, which is an extension of the conventional analytical cell-based model, to figure out the physical process of the extrinsic-defect formation. The results analyzed using the model revealed that the extrinsic defects are formed in the SiON films in the case when the number of normal cells in a vertical arrangement becomes equal to or smaller than the threshold value of 3 or 4.