Toshiyuki Kikuchi

A 0.2-/spl mu/m bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors

A 0.2-/spl mu/m bipolar-CMOS process technology on a bonded SOI wafer was developed for ultra-high-speed applications. This process was used to fabricate a new cache memory chip consisting of 9-Mb 0.6-ns SRAMs and a 200-K 25-ps ECL gate array. To achieve high performance, the 0.2-/spl mu/m bipolar-CMOS process features a 6-/spl mu/m/sup 2/-cell-size BJT with a 50-nm base width, a 6T-CMOS memory cell and copper interconnects that reduce wiring delay by 30%. A combination of low-energy ion-implantation and two-step annealing was applied to form a low-leakage, shallow base junction. A bonded SOI wafer with deep and shallow trench isolations was used to maximize the BJT performance.

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

We have developed a wafer-scale layer-transfer technique for transferring GaAs and Ge onto Si wafers of up to 300 mm in diameter. Lattice-matched GaAs or Ge layers were epitaxially grown on GaAs wafers using an AlAs release layer, which can subsequently be transferred onto a Si handle wafer via direct wafer bonding and patterned epitaxial lift-off (ELO). The crystal properties of the transferred GaAs layers were characterized by X-ray diffraction (XRD), photoluminescence, and the quality of the transferred Ge layers was characterized using Raman spectroscopy. We find that, after bonding and the wet ELO processes, the quality of the transferred GaAs and Ge layers remained the same compared to that of the as-grown epitaxial layers. Furthermore, we realized Ge-on-insulator and GaAs-on-insulator wafers by wafer-scale pattern ELO technique.

A 0.35 /spl mu/m ECL-CMOS process technology on SOI for 1 ns mega-bits SRAMs with 40 ps gate array

A 0.35 /spl mu/m ECL-CMOS technology has been developed to achieve high speed and high density LSIs for mainframe computers. A high speed bipolar transistor with cutoff frequency f/sub T/ of 30 GHz and a 30 /spl mu/m/sup 2/ 6T-CMOS memory cell with a trench isolation are introduced onto an SOI substrate. This technology has been applied to a 40 ps, 120 K gate logic LSI and a 1 ns, 2.3 Mbit SRAM with 50 K gate array.

Reduction of Base Resistance and Increase in Cutoff Frequency of Si Bipolar Transistor Using Rapid Vapor-Phase Doping

The shallow intrinsic base region of a double poly-Si self-aligned bipolar transistor was formed by rapid vapor-phase doping (RVD) in order to increase the high-frequency performance, compared to that provided by low-energy BF2 ion implantation. RVD produced a transistor with fT of 50-GHz and rb of 400-Ω. These parameters are 20% higher and 15% lower than those of a transistor produced by BF2 implantation. Low base resistance also led to an increase in the maximum oscillation frequency fmax to over 40 GHz in transistors with longer emitter. A two-dimensional profile simulation clarified that RVD can form a shallower intrinsic base profile and a deeper link base profile than those formed by BF2 ion implantation. These doping profiles made it possible to increase fT and fmax, and to reduce rb simultaneously.

15-ps ECL/74-GHz f/sub T/ Si bipolar technology

A very high performance Si bipolar transistor technology has been developed. In-situ phosphorus doped polysilicon (IDP) emitter technology was used to reduce the thermal budget and emitter resistance. Very thin bases were obtained by rapid vapor-phase doping (RVD) and low energy BF2/sup +/ ion implantation. Double-polysilicon self-aligned bipolar technology with U-groove isolation on bonded SOI wafers was used to reduce the parasitic capacitances. Using these key techniques, a minimum ECL gate delay time of 15 ps and a cut-off frequency of 74 GHz have been achieved.<<ETX>>

A new vertically stacked poly-Si MOSFET for 533 MHz high speed 64Mbit SRAM

A new vertically stacked poly-Si MOSFET has been studied as a novel technique that enables device integration without applying advanced node process. Reduced cell area size of 1.21 /spl mu/m/sup 2/ has been achieved in 6T-SRAM which is 60% of 130 nm node based planer type cell. Operation speed of 533 MHz was also confirmed.

Atomic Layer Control for Suppressing Extrinsic Defects in Ultrathin SiON Gate Insulator of Advanced Complementary Metal–Oxide–Semiconductor Field-Effect Transistors

By measuring the minimum supply voltage for normal operation of test random access memories, we detected low-density extrinsic defects in silicon-oxynitride (SiON) gate insulators that were formed by state-of-the-art technologies. The density of the detected defects had a strong correlation with optical thickness dopt, which was ellipsometrically measured, regardless of the processing conditions of the SiON films. We propose to maintain the dopt above a threshold value of 1.7 nm to suppress the problems caused by the defects. The optimization of post nitridation annealing (PNA) condition is promising for meeting the criterion without sacrificing device performance. By elaborate investigations based on the Clausius–Mosotti relation, we found that the optical thickness of SiON films is approximately proportional to the atomic area density in the films. On the basis of this finding, we developed a model, which is an extension of the conventional analytical cell-based model, to figure out the physical process of the extrinsic-defect formation. The results analyzed using the model revealed that the extrinsic defects are formed in the SiON films in the case when the number of normal cells in a vertical arrangement becomes equal to or smaller than the threshold value of 3 or 4.

Large-scale Ge-on-Insulator wafers using low-temperature bonding and Epitaxial Lift-Off (ELO) technique

We have realized patterned Ge-on-Insulator wafers by large-scale layer transfer technology. In conjunction with low-temperature bonding and patterned Epitaxial Lift-Off (ELO) technique, high quality Ge layer transfer was achieved in full-wafer scale.