Satwik Patnaik

Understanding the Transient Behavior of Injection Locked LC Oscillators

An analytical framework has been developed to describe the transient behavior of negative resistance injection-locked oscillators based on Adlers equation. Design insights are provided by using a combination of analytical simplifications and graphical interpretation. It has been shown that injection locking can be used to meet the requirements for fast hopping systems like the MBOA-UWB specification. The theoretical analysis and design solutions have been verified by extensive simulations on real CMOS processes.

Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-

This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, based on this technique, is a CMOS-only implementation and has been fabricated in a 0.13-μm SiGe BiCMOS process. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of -114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5°. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm2 and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.

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This paper presents a simple, unified phase noise model for injection-locked oscillators (ILO). We show that an ILO is identical to a type-I first-order PLL in its noise behavior within the lock range. The model predicts the phase noise of injection-locked oscillators (ILO), injection-locked frequency dividers (ILFD), and injection-locked frequency multipliers (ILFM) as a function of the injection source phase noise and the oscillator phase noise. Measurement results from a discrete 57MHz Colpitts ILO, an integrated 6.5GHz ILFD, and an integrated 24GHz ILFM are presented to validate the theoretical predictions.

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This paper reports the first analog integrated spatio-spectral beamforming front-end. The proposed front-end allows for accurate beam steering of signals with large fractional bandwidths, thus minimizing beam squinting, and simultaneous and independent steering of multi-carrier signals. Different spatio-spectral beamforming strategies are discussed and compared. As a proof of concept, an 8 GHz 2-channel, 4-frequency phased-array beamformer is designed and implemented in 65 nm CMOS. The IF signal on each channel is frequency split using an all passive 4-point analog FFT. The orthogonal frequency outputs are then beam-steered using an all passive I-Q vector-combiner. The RF circuit draws 22.8 mA from a 1.2 V supply while the analog baseband consumes 135 μW at 120 MS/s (9 pJ/conv.).

A simple, unified phase noise model for injection-locked oscillators

Phased arrays have long been used by the military for radar applications, but have only been recently applied to consumer applications. In a phased array system, one or more narrow beams are generated by transmitting (or receiving) a common RF signal that is phase shifted at the output of each antenna in the array such that the direction of the beams can be varied by controlling the phase difference between consecutive antennas. Microwave transceivers for phased-array radar applications have traditionally been fabricated in III–V technologies like GaAs and InP due to their superior ƒT and ƒmax. However, modern-day CMOS and BiCMOS technology nodes are now exhibiting ƒT and ƒmax in the range of 200 to 250GHz, tipping the scales in favor of silicon due to its higher integration capability, lower costs and the availability of significant digital signal processing. Recent designs in CMOS have shown its capability to handle millimeter-wave frequencies [1–3].

Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays

We present a novel injection locking frequency generation scheme for UWB systems. In the MBOA-UWB specification, the critical constraint on the frequency synthesizer is the band switching time (< 9.5 ns). In this paper we derive analytical expressions for the transient behavior of injection locked oscillators (ILO) and describe the design constraints on frequency settling of ILOs. We show that they are capable of UWB compliant fast frequency hopping. ILO based frequency synthesizers have a number of advantages over traditional fast hopping LO generation techniques. In particular, it eliminates the need for multiple PLLs and single-sideband (SSB) mixers reducing power consumption and eliminating parasitic spurs.

A dual-mode architecture for a phased-array receiver based on injection locking in 0.13µm CMOS

In this paper we present the design for a fast hopping frequency synthesizer with sub-10 ns switching time capability. The synthesizer utilizes injection-locking to obtain the fast lock time. The measurement results from a prototype design fabricated in 0.13-mum CMOS, shows good agreement with theoretical results. Minimum frequency hopping time at 3.3 GHz is 4 ns while the worst case is 10.02 ns. The injection-locked oscillator (ILO) system consumed 10 mA of current from a 1.2 V supply.

Fast Hopping Injection Locked Frequency Generation for UWB

This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, based on this technique, is a CMOS-only implementation and has been fabricated in a 0.13-μm SiGe BiCMOS process. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of -114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5°. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm2 and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.

Sub-10ns Frequency Hopping Synthesizer based on Injection-Locking

This paper presents a 24-GHz two-channel phased-array receiver. The receiver adopts the LO-phase-shifting approach and employs a sub-harmonically injection-locked phase-shifter. A CMOS-only prototype, fabricated in a 130-nm SiGe BiCMOS technology, draws 16-mA of current from a 1.5-V supply and consists of a injection-locked oscillator (operating as a phase-shifter, LO-buffer and frequency multiplier), a down-conversion mixer and an IF-buffer. The worst-case measured amplitude and phase errors are 1.5-dB and 4°. The two-channel receiver occupies an active area of 0.23-mm2.

A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology

A novel multi-frequency beamforming front-end is proposed. The proposed front-end allows for simultaneous and independent steering of multiple frequency beams. As proof of concept, an 8GHz 2-channel, 4-frequency phased array beam-former is designed and implemented in 65nm CMOS. The IF signal on each channel is frequency split using an all passive 4-point analog FFT. The orthogonal frequency outputs are then beam steered using an all passive I-Q vector combiner. The RF circuit draws 22.8mA from a 1.2V supply while the analog baseband consumes 9pJ/conv. (135μW at 120MSps).