Bodhisatwa Sadhu

A Linearized, Low-Phase-Noise VCO-Based 25-GHz PLL With Autonomic Biasing

This paper describes a new approach to low-phasenoise LC VCO design based on transconductance linearization of the active devices. A prototype 25 GHz VCO based on this linearization approach is integrated in a dual-path PLL and achieves superior performance compared to the state of the art. The design is implemented in 32 nm SOI CMOS technology and achieves a phase noise of - 130 dBc/Hz at a 10 MHz offset from a 22 GHz carrier. Additionally, the paper introduces a new layout approach for switched capacitor arrays that enables a wide tuning range of 23%. More than 1500 measurements of the PLL across PVT variations were taken, further validating the proposed design. Phase noise variation across 55 dies for four different frequencies is σ < 0.6 dB. Also, phase noise variation across supply voltages of 0.7-1.5 V is 2 dB and across 60 °C temperature variation is 3 dB. At the 25 GHz center frequency, the VCO FOMT is 188 dBc/Hz. Additionally, a digitally assisted autonomic biasing technique is implemented in the PLL to provide a phase noise and power optimized VCO bias across frequency and process. Measurement results indicate the efficacy of the autonomic biasing scheme.

A CMOS 3.3-8.4 GHz wide tuning range, low phase noise LC VCO

A novel inductor switching technique is used to design and implement a wideband LC voltage controlled oscillator (VCO) in 0.13µm CMOS. The VCO has a tuning range of 87.2% between 3.3 and 8.4 GHz with phase noise ranging from −122 to −117.2 dBc/Hz at 1MHz offset. The power varies between 6.5 and 15.4 mW over the tuning range. This results in a Power-Frequency-Tuning Normalized figure of merit (PFTN) between 6.6 and 10.2 dB which is one of the best reported to date.

A fully-integrated dual-polarization 16-element W-band phased-array transceiver in SiGe BiCMOS

This paper presents a multi-function, dual-polarization phased array transceiver supporting both radar and communication applications at W-band. 32 receive elements and 16 transmit elements with dual outputs are integrated to support 16 dual polarized antennas in a package. The IC further includes two independent 16:1 combining networks, two receiver downconversion chains, an up-conversion chain, a 40GHz PLL, an 80GHz frequency doubler, extensive digital control circuitry, and on-chip IF/LO combining/distribution circuitry to enable scalability to arrays at the board level. The fully-integrated transceiver is fabricated in the IBM SiGe BiCMOS 0.13um process, occupies an area of 6.6×6.7mm2, and operates from 2.7V (analog/RF) and 1.5V (digital) supplies. Multiple operating modes are supported including the simultaneous reception of two polarizations with a 10GHz IF output, transmission in either polarization from an IF input, or single-polarization transmission/reception from/to I&Q base-band signals (2.5W RX, 2.9W TX). Measurement results show 8dB receiver NF and 2dBm transmitter output power per element at 94GHz in both polarizations.

Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS

This work describes the design of a 16 point analog domain FFT using a Charge Re-use Analog Fourier Transform (CRAFT) engine. The circuit relies on charge re-use to achieve 47 dB average output SNDR on an instantaneous input bandwidth of 5 GHz, and consumes only 3.8 mW (12.2 pJ/conv.). The CRAFT engine is used as a wide-band, low power RF front-end channelizer for software defined radio (SDR) applications. The paper also discusses the handling of circuit non-idealities for the CRAFT design: their significance, modeling, and circuit techniques for their mitigation. These techniques enable this implementation to achieve a large dynamic range even at high speeds.

-Band Dual-Polarization Phased-Array Transceiver Front-End in SiGe BiCMOS

This paper discusses the design and implementation of a 94-GHz phased-array transceiver front-end in SiGe BiCMOS that is capable of receiving concurrently in both vertical (V) and horizontal (H) polarizations and time-duplexed transmission in either polarization. The compact front-end is implemented in 1.3 mm× 1.45 mm of silicon area to ensure compatibility with a scalable phased-array tile approach with λ/2 ( ~ 1.6 mm) spacing between elements. Each transceiver front-end includes variable transmitter (TX) and receiver (RX) gain and 360° variable phase shift in TX and RX. Co-integration of the transmit-receive (T/R) switch with the power amplifier (PA) and low-noise amplifier (LNA) matching network minimizes switch impact on RX noise figure (NF). A varactor-based passive reflection-type phase shifter (RTPS) is shared between the TX and RX to reduce area. Analysis of loss mechanisms in on-chip RTPS leads to a novel RTPS load that minimizes RTPS loss while ensuring that the amplitude variation across phase shift is . In RX mode, the front-end achieves 30-dB RX gain, bandwidth of 15 GHz (84-99 GHz) with 10-dB NF in the high-gain mode. In TX mode, the front-end achieves >2-dBm saturated output power and >0-dBm output-referred 1-dB compression point (OP1dB) in V and H polarizations (time-duplexed), 30-dB gain, and 8-GHz bandwidth (89-97 GHz). The 94-GHz phase shifters achieve full 360° variable phase shift with 5-bit phase resolution (11.25° resolution) and error and 1-dB rms gain error at 94 GHz. The front-end consumes 160 mW in RX mode for dual-polarization concurrent reception/phase-shifting and 116 mW in TX mode for time-duplexed V and H output in the W-band.

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL

An integral-path self-calibration scheme is introduced as part of a 20.1 GHz to 26.7 GHz low-noise PLL in 32 nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCOs small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4 dB to 1 dB, when measured at 70 sites on a 300 mm wafer. The PLL has a measured phase noise @10 MHz offset of -126.5 dBc/Hz at 20.1 GHz and - 124.2 dBc/Hz at 24 GHz

7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication

Next-generation mobile technology (5G) aims to provide an improved experience through higher data-rates, lower latency, and improved link robustness. Millimeter-wave phased arrays offer a path to support multiple users at high data-rates using high-bandwidth directional links between the base station and mobile devices. To realize this vision, a phased-array-based pico-cell must support a large number of precisely controlled beams, yet be compact and power efficient. These system goals have significant mm-wave radio interface implications, including scalability of the RFIC+antenna-array solution, increase in the number of concurrent beams by supporting dual polarization, precise beam steering, and high output power without sacrificing TX power efficiency. Packaged Si-based phased arrays [1–3] with nonconcurrent dual-polarized TX and RX operation [2,3], concurrent dual-polarized RX operation [3] and multi-IC scaling [3,4] have been demonstrated. However, support for concurrent dual-polarized operation in both RX and TX remains unaddressed, and high output power comes at the cost of power consumption, cooling complexity and increased size. The RFIC reported here addresses these challenges. It supports concurrent and independent dual-polarized operation in TX and RX modes, and is compatible with a volume-efficient, scaled, antenna-in-package array. A new TX/RX switch at the shared antenna interface enables high output power without sacrificing TX efficiency, and a t-line-based phase shifter achieves <1° RMS error and <5° phase steps for precise beam control.

W-band scalable phased arrays for imaging and communications

This article discusses the benefits and challenges associated with the design of multi-function scalable phased arrays at millimeter wave frequencies. First, applications for phased arrays with tens to hundreds of elements are discussed. Existing solutions for scaling silicon-based phased arrays from microwave to terahertz frequencies are reviewed. The challenges and tradeoffs associated with multiple integration options for W-band phased arrays are analyzed, with special consideration given to packaging and antenna performance. Finally, a solution based on SiGe ICs and organic packages for a 64-element dual-polarized 94 GHz phased array is described, along with associated measurement results.

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

On-chip analog self-healing requires low-cost sensors to accurately measure various performance metrics. In this paper we propose a novel approach of indirect performance sensing based upon Bayesian model fusion (BMF) to facilitate inexpensive-yet-accurate on-chip performance measurement. A 25GHz differential Colpitts voltage-controlled oscillator (VCO) designed in a 32nm CMOS SOI process is used to validate the proposed indirect performance sensing and self-healing methodology. Our silicon measurement results demonstrate that the parametric yield of the VCO is improved from 0% to 69.17% for a wafer after the proposed self-healing is applied.

A simple, unified phase noise model for injection-locked oscillators

This paper presents a simple, unified phase noise model for injection-locked oscillators (ILO). We show that an ILO is identical to a type-I first-order PLL in its noise behavior within the lock range. The model predicts the phase noise of injection-locked oscillators (ILO), injection-locked frequency dividers (ILFD), and injection-locked frequency multipliers (ILFM) as a function of the injection source phase noise and the oscillator phase noise. Measurement results from a discrete 57MHz Colpitts ILO, an integrated 6.5GHz ILFD, and an integrated 24GHz ILFM are presented to validate the theoretical predictions.