Anzhela Yu. Matrosova

Path delay faults and ENF

Single path delay faults (PDFs) are considered. They are reduced to temporal faults of ENF literals. These temporal faults exist during delay time of the relevant paths and then disappear. Deriving test pair v1, v2 for robust and non-robust PDFs is based on analyses of products of free fault and fault ENF. Some properties of these test pairs are determined. Possibilities of using these properties to cut the length of the test detecting all PDFs of a combinational circuit are shown.

Survivable self-checking sequential circuits

This paper presents a method for designing totally self-checking synchronous sequential circuits (SSC), and investigates their behavior in presence of transient faults. We deal with the case when the circuit is able to recover after the number of clocks. We call SSC owing this property as a survivable SSC. A concept of a partially monotonous SSC is developed in the paper. It is proven that the partially monotonous SSCs are survivable.

Self-checking FSM design with observing only FSM outputs

We deal with the problem of a self-checking FSM design with observing only FSM outputs. We suggest a special PLA description of the FSM behavior that is well suited in practice. It is established that a factorized multilevel synthesis method applied to this PLA description and followed by the gate implementation provides observing only FSM outputs. We assume that a set of faults considered does not demand introducing additional FSA input lines. We also propose a mathematical tool that makes possible for any synthesis method applied to this special PLA description to clarify the possibility of observing only FSM outputs.

Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBs

A combinational circuit is derived with covering the proper Shared ROBDD by CLBs in the frame of FPGA technology. Single stuck-at faults at the CLBs poles and multiple faults constituted from such single stuck-at faults are considered. It is shown that the test pattern as for single stuck-at fault so for multiple fault there always exists. The test pattern for a multiple fault is the special test pattern for the special single stuck-at fault forming the multiple one. Test for all multiple faults is derived from any test for all single stuck-at faults. The length of the multiple faults test is linear function of the single faults test length. A multiple fault test is the one of high quality. In particular SEU and bridge faults may manifest themselves as multiple faults at the CLBs poles. Deriving test for all multiple faults was executed for the certain bench-marks. For them the length of the multiple faults test is about the twice length of the single faults test.

Survivable discrete circuits design

Schemes providing a synchronous sequential circuit (SSC) or combinational circuit (CC) survivability for unidirectional transient and intermittent faults are suggested. They are based on doubling self-checking circuits with using a self-testing checker for one of them and masking a fault manifestation with OR, AND and MX circuits. The schemes ensure a correct behavior when any scheme permissible fault occurs. We mean single stuck-at faults at gates poles and d flip-flops poles of the scheme. A method of cutting overhead during survivable self-checking SSC design is proposed. It is oriented to only transient faults.

Generating all test patterns for stuck-at faults at a gate pole and their connection with the incompletely specified Boolean function of the corresponding subcircuit

The algorithm of generating all test patterns for a stuck-at fault at a gate pole of single-output combinational circuit is suggested. It is based on the method of redefining products suggested before. It is known that a behavior of a subcircuit of a combinational circuit is presented by the incompletely specified Boolean function. It means that there are the input Boolean vectors of a circuit on which the value of the subcircuit output has no effect on the value of the circuit output. It is set up that the on-set vectors of a subcircuit incompletely specified Boolean function are represented by all test patterns for the stuck-at 0 fault at a subcircuit output and the off-set vectors are represented by all test patterns for the stuck-at 1 fault at the same output. This result may be used for structural combinational circuit minimizing and for partially programmable circuit design. The experimental results are presented.

PDF testability of the circuits derived by special covering ROBDDs with gates

Circuits obtained by covering ROBDD nodes with special gate subcircuits are considered. Formulae derived from their structural descriptions are investigated. Based on the results of investigations algorithms of deriving test pairs for robust testable PDFs and validatable non robust testable PDFs of such circuits are developed. Possibilities of cutting calculations under finding the longest circuit paths are discussed.

Designing FPGA based self-testing checkers for m-out-of-n codes

The paper describes a specific method for designing self-checking checkers for m-out-of-n codes. The method is oriented to the field programmable gate arrays technology and is based on decomposing the sum-of-minterms corresponding to an m-out-of-n code. The self-testing property of the proposed checker is proven for a set of multiple stuck-at faults at input and output poles of a logic cell. An estimated complexity of obtained m-out-of-n checker demonstrates high efficiency of the proposed method.

ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself

Methods of revealing of transfer sequence existence of the length not more l for a set of states (internal states) without deriving the sequence itself and finding the shortest transfer sequence of the length not more l for a sequential circuit are developed. The methods are based on applying operations either on full ROBDDs, representing transition functions or fragments of these ROBDDs. Multiplications of the proper ROBDDs are executed with using full ROBDDs but summations - with using ROBDDs fragments. It is setup that for revealing transfer sequence existence we may use ROBDDs fragments depending on only state variables. When finding the shortest sequence we use ROBDDs so that each path originated by state variables has the only prolongation among input variables. The initial state of a sequential circuit is given. Set M0 of states one of which has to be reached is represented by the ROBDD.

Delay testable sequential circuit designs

New method of a sequential circuit design based on using mixed description of the circuit behavior is suggested. A combinational part behavior of a sequential circuit is represented with the composition of ROBDDs (Reduced Ordered Binary Decision Diagrams) and monotonous products. The method provides fully delay testability of a combinational part of a sequential circuit. Algorithms of deriving test pairs for robust PDFs (Path Delay Faults) are suggested. The method is oriented to cut the path lengths of the obtained circuits.