Satyaki Das

A 90nm low-power FPGA for battery-powered applications

Programmable logic devices such as field-programmable gate arrays (FPGAs) are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than application-specified integrated circuits and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered applications. Our design is based on a commercial low-cost FPGA and achieves substantial power savings through a series of power optimizations. The resulting architecture is compatible with existing commercial design tools. The implementation is done in a 90-nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode and wakes up from standby mode in approximately 100 ns

A 90-nm Low-Power FPGA for Battery-Powered Applications

Programmable logic devices such as field-programmable gate arrays (FPGAs) are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than application-specified integrated circuits and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered applications. Our design is based on a commercial low-cost FPGA and achieves substantial power savings through a series of power optimizations. The resulting architecture is compatible with existing commercial design tools. The implementation is done in a 90-nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode and wakes up from standby mode in approximately 100 ns

Determination of Power Gating Granularity for FPGA Fabric

In this study, we present a design methodology to determine the granularity of power gating for field programmable gate arrays (FPGAs). Fine-grain power gating is more effective than coarse-grain power gating to reduce the active leakage power of unused logic and interconnection resources. However, the area overhead in fine-grain power gating is higher than that of coarse-grain power gating. Based on the placement and routing of benchmark designs in Spartan-3trade-like FPGA, guidelines for determining the granularity of power gating are provided. It is found that programmable resources with low utilization can be power gated more coarsely than the resources with high utilization

Heterogeneous routing architecture for low-power FPGA fabric

In this study, we present design techniques to implement low power FPGA routing architecture by combining fast and slow routing resources, where the circuit design of slow resource is optimized to reduce leakage power. Timing-driven placement and routing experiments along with power modeling are used to identify the type and percentage of resources that can be slowed down. Based on our analysis, we present a heterogeneous (HT) routing architecture to reduce standby power dissipation of FPGA routing fabric by 33% without any area penalty and at the cost of less than 5% performance degradation.

Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates

Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the. programmable logic block (PLB) to reduce area and power and increase performance in FP-GAs. However, it is unclear whether incorporating macro-gates with wide inputs inside PLBs is beneficial. In this paper, we first propose a methodology to extract a small set of logic functions that are able to implement a large portion of functions for given FPGA applications. Assuming that the extracted logic functions are implemented by macro-gates in PLBs, we then develop a complete synthesis flow for such heterogeneous PLBs with mixed LUTs and macro-gates. The flow includes a cut-based delay and area optimized technology mapping, a mixed binary integer and linear programming based area recovery algorithm to balance the resource utilization of macro-gates and LUTs for area-efficient packing, and a SAT-based packing. We finally evaluate the proposed heterogeneous FPGA using the newly developed flow and show that mixing LUT and macro-gates, both with 6 inputs, improves performance by 16.5% and reduces logic area by 30% compared to using merely 6-input LUTs.

Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate

Small gates, such as AND2, XOR2, and MUX2, have been mixed with lookup tables (LUTs) inside programmable logic blocks (PLBs) to reduce area and power and increase performance in FPGAs. However, it is unclear whether incorporating macrogates with wide inputs inside PLBs is beneficial. In this paper, we first develop a methodology to extract a small set logic functions that are able to implement a large portion of functions for given FPGA applications, and propose a heterogeneous PLB with one LUT and one macrogate for the selected logic functions. Furthermore, we develop a synthesis flow for such heterogeneous PLBs, including a cut-based delay and area optimized technology mapping, a mixed binary integer and linear programming-based postmapping area recovery to balance the utilization of macrogates and LUTs, and a SAT-based PLB architecture-aware packing. Experiments using over 70 industrial benchmark applications show that we can extract four six-input logic functions to cover more than 50% functions of these applications, and the proposed synthesis flow reduces area by 5% compared to an alternative flow without the postmapping area recovery when both have the optimal logic depth. Compared to the PLB with mixed LUT-4 and small macrogates (XOR2 and MUX2), the PLB with mixed LUT-4 and four-input macrogate reduces logic depth by 6% (and up to 42%) for the aforementioned applications.