Austin H. Lesea

The rosetta experiment: atmospheric soft error rate testing in differing technology FPGAs

Results are presented from real-time experiments that evaluated large field programmable gate arrays (FPGAs) fabricated in different CMOS technologies (0.15 /spl mu/m, 0.13 /spl mu/m, and 90 nm) for their sensitivity to radiation-induced single-event upsets (SEUs). These results are compared to circuit simulation (Qcrit) studies as well as to Los Alamos Neutron Science Center (LANSCE) neutron beam results and Crocker Nuclear Laboratory (University of California, Davis) cyclotron proton beam results.

Effectiveness of Internal Versus External SEU Scrubbing Mitigation Strategies in a Xilinx FPGA: Design, Test, and Analysis

A comparison of two scrubbing mitigation schemes for Xilinx field programmable gate array devices is presented. The design of the scrubbers is briefly discussed along with an examination of mitigation limitations. Heavy ion data are then presented and analyzed.

Monte-Carlo Based On-Orbit Single Event Upset Rate Prediction for a Radiation Hardened by Design Latch

Heavy ion cross section data taken from a hardened-by-design circuit are presented which deviate from the traditional single sensitive volume or classical rectangular parallelepiped model of single event upset. TCAD and SPICE analysis demonstrate a SEU mechanism dominated by multiple node charge collection. Monte Carlo simulation is used to model the response and predict an on-orbit error rate.

Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)

Heavy-ion irradiation and fault injection experiments were conducted to evaluate the upset sensitivity of the Xilinx Virtex-II field programmable gate arrays (FPGAs) input/output block (IOB). Full triple module redundancy (TMR) of the IOBs, in combination with regular configuration scrubbing, proved to be a quite effective upset mitigation method.

Qualification Methodology for Sub-Micron ICs at the Low Noise Underground Laboratory of Rustrel

Alpha contamination has become a major concern in ICs. To qualify packaging solutions for commercial, industrial, and aerospace/defense components, a program is described. The chosen methodology associates the use of real time testing in altitude and underground environments. Experiments are performed on Xilinx FPGAs. Goals, experiment design, statistical confidence, initial results are analyzed and discussed.

Analysis of within-die process variation in 65nm FPGAs

FPGAs are a great platform for studying within-die process variation because test structures can be implemented in product silicon using reconfigurable logic. This approach can achieve very high coverage without wasting otherwise useful silicon area. In this paper, we present a detailed analysis of within-die delay variation in a 65nm FPGA. We use densely distributed test oscillators to measure within-die performance variation across a large sample of dies, and identify both random and spatially correlated systematic components through post-processing. Finally, we evaluate the benefit of modeling within-die systematic variation in static timing analysis.

Experimental study and analysis of soft errors in 90nm Xilinx FPGA and beyond

The Xilinx methodology used for soft error test and measurement in FPGAs is exposed. The technology scaling impact on SER from 250 nm down to 65 nm is presented and analyzed by comparing beam and real time testing. Some trends are presented and analyzed.

Circuit Effect on Collection Mechanisms Involved in Single Event Phenomena: Application to the Response of a NMOS Transistor in a 90 nm SRAM Cell

SEU is studied in a 90 nm SRAM cell with different simulation approaches. The SRAM cell main SEU parameters (maximum current peak, collected charge, threshold LET) are extracted and compared. It is shown that the simulation conditions have a direct impact on the cell behavior and so on the SEU prediction. Moreover, not accounting for voltage variations induced by the particle generation in the circuit results in an overestimation of struck drain current.

Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I/O's Using Fault Injection on SRAM Based FPGAs

Fault-injection experiments on Virtex-IItrade FPGAs quantify failure and degradation modes in I/O channels incorporating triple module redundancy (TMR). With increasing frequency (to 100 MHz), full TMR under both I/O standards investigated (LVCMOS at 3.3V and 1.8V) shows more configuration bits have a measurable detrimental performance effect when in error

Effect of multiple injections on the SEEs in SRAM cell

This paper presents a new approach to analyze nanometres SRAM response to SEE attributed to proton-Silicon interactions. It couples the MUlti SCAles Single-Event Phenomena Predictive Platform (MUSCA SEP3) with SPICE modelling to study multi-injections phenomena.