Satyamurthy Pullela

Skew And Delay Optimization For Reliable Buffered Clock Trees

Recenily, seveml design auiomaiion approaches for delay and skew minimization of clock nets have been proposed. These approaches are based upon varying the widths and lengths of the clock tree wires io minimize skew and sometimes delay. Most of these iechniques do noi consider the clock iree power dissipation, occupied area, or the reliabiliiy of ihe resvlts with regard to the ineviiable process variations. In this paper, concurreni buffer insertion and global wire width adjusimenis are used to reliably reduce both delay and power from that obtained for a reliable buflerless soluiion. Moreover, in spite of ihe belief ihai ihe mismaich in bufler delays can resuli in significant clock skew, our resulis show ihai buflers can actually reduce the process dependent skew for a reliable design.

Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization

Recognizing that routing constraints and process variations make non-zero skew inevitable, this paper describes a novel methodology for constructing reliable low-skew clock trees. The algorithm efficiently calculates clock-tree delay sensitivities to achieve a target delay and a target skew. Moreover, the sensitivities also show that wires should be widened as opposed to lengthened to reduce skew since the former improves reliability while the latter reduces it. This paper introduces the concept of designing reliable clock nets with process-insensitive skew.

Library-less synthesis for static CMOS combinational logic circuits

Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield good synthesis results over many blocks or even for an entire chip. Consequently this approach precludes an optimal design of individual blocks which may need custom structures. The authors present a new transistor level technique that optimizes CMOS circuits both structurally and size-wise. The technique is independent of a library and hence can explore a design space much larger than that possible due to gate level optimization. Results demonstrate a significant improvement in circuit performance of the resynthesized circuits.

RC interconnect synthesis—a moment fitting approach

Presently, delays due to the physical interconnect between logic gates account for large portions of the overall path delays. For this reason, synthesis of the logic gate fanout structure is of paramount importance during performance optimization. This paper presents a methodology for on-chip RC interconnect synthesis. Moment sensitivities are used to vary the wire widths of the branches in an RC interconnect tree to achieve performance targets. In this paper, signal slopes and delays at critical fanout nodes are the targets, and the impact on total metal area is considered. An O(MN 2 ) procedure for computing the exact moment sensitivities in an RC tree is described.

Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets

Sensitivity-based methods for wire sizing have been shown to be effective in reducing clock skew in routed nets. However, lack of efficient sensitivity computation techniques and excessive space and time requirements often limit their utility for large clock nets. Furthermore, most skew reduction approaches work in terms of the Elmore delay model and, therefore, fail to balance the signal slopes at the clocked elements. In this paper, we extend the sensitivity-based techniques to balance the delays and signal-slopes by matching several moments instead of just the Elmore delay. As sensitivity computation is crucial to our approach, we present a new path-tracing algorithm to compute moment sensitivities for RC trees. Finally, to improve the runtime statistics of sensitivity-based methods, we also present heuristics to allow for efficient handling of large nets by reducing the size of the sensitivity matrix.

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization

With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Instead of sizing only the gates along the critical paths for delay reduction, the trade-off possible by simultaneously sizing gate and interconnect must also be considered. We show that for optimal gate and interconnect sizing, it is imperative that the interaction between the driver and the RC interconnect load be taken into account. We present an iterative sensitivity-based approach to simultaneous gate and interconnect sizing in terms of a gate delay model which captures this interaction. During each iteration, the path delay sensitivities are efficiently calculated and used to size the components along a path.

Transistor-level sizing and timing verification of domino circuits in the Power PC/sup TM/ microprocessor

This paper describes a tool called Focus that is currently being used for the timing verification and siting of domino CMOS circuits in a Power PC/sup TM/ microprocessor. Domino CMOS circuits introduce more complex timing and sizing requirements compared to conventional static circuits. This paper shows how these requirements are addressed in Focus. Some case studies involving the application of Focus on production circuits are also described.

Low power IC clock tree design

When reliability to process variations becomes an important issue, wires in the clock-tree must be made extremely wide to limit the process skew to a specified tolerable value. Due to the resultant increase in the overall capacitance, the power dissipation in clock-net is dramatically increased. We demonstrate that in spite of buffer mismatches and an additional component of power dissipation due to their short-circuit currents, the clock tree power can be significantly reduced by buffer insertion given the constraint on allowable process-variation dependent skew and maximum current densities (electromigration).

Skew reduction in clock trees using wire width optimization

A novel technique for designing binary clock trees with reduced delay and near-zero skew is described. Starting with the minimum possible metal pitch for the tree branches, the proposed algorithm increases the width of selected branches using a set of skew reduction heuristics. A technique to deterministically reduce the phase delay by varying the widths of the main branches is also described. The main advantage of the proposed technique is the decoupling of the clock-net routing from the skew reduction phase. This makes it possible to route the clock net taking macro blockages into account, an important need in todays design methodologies. A router which yields a binary-tree route can be used. A simple method to reduce the delay of a clock net arbitarily is also shown. A new criterion in clock net synthesis, i.e., robustness, is also introduced.

Post-processing of clock trees via wiresizing and buffering for robust design

Achieving near-zero skew for a large clock tree is generally at the expense of adding large amounts of metal interconnect. This added metal can significantly increase the total clock-net capacitance, thereby increasing the power dissipation in proportion. In addition, it is shown that it becomes increasingly difficult to control clock-signal skew due to metal-wiring process variations as the total clock-net capacitance increases. In this paper we demonstrate that buffer insertion can be used to reduce the total capacitance, hence the power, while generating a design which is as robust as one with no intermediate buffering. Moreover, delays are reduced substantially as well. Given an initial feasible route with constraints. On wire widths, wire sizing and buffer insertion are performed concurrently at each iteration of optimal buffer location search. Statistical process variations of the buffers, their loads, and the metal interconnect parameters are considered as part of the robust design process.