Satyen Mukherjee

Realization of high breakdown voltage (>700 V) in thin SOI devices

The avalanche breakdown voltage of silicon on insulator (SOI) lateral diodes is investigated theoretically and experimentally. Theoretically, a condition is derived for achieving a uniform lateral electric field and thus optimizing the breakdown voltage. Using this condition, it is shown that, for SOI thicknesses below about 1 mu m, diode breakdown voltage increases with decreasing SOI layer thickness. Experimentally, breakdown voltages in excess of 700 V have been demonstrated for the first time on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers. The results obtained demonstrate the feasibility of making high-voltage thin-film SOI LDMOS transistors and, more importantly, the ability to integrate such devices with high-performance ultra-thin SOI CMOS circuits on a single chip.<<ETX>>

A single transistor EEPROM cell and its implementation in a 512K CMOS EEPROM

This paper describes an electrically programmable and erasable nonvolatile memory cell employing a single floating gate transistor (1), and its implementation in a 512K CMOS EEPROM memory chip. The single transistor EEPROM cell is based on an innovative device concept, and utilizes proven process techniques. The cell is programmed to a high Vt state by channel hot electron injection like an EPROM cell, and erased to a low Vt state by Fowler Nordheim tunneling from the floating gate to source diffusion. With the proper choice of gate dielectric and cell layout the cell is programmed to high threshold with less than 5 volts on the drain and less than 15 volts on the control gate. Erasing is achieved with less than 15 volts on the source diffusion. A 25 square micron cell has been implemented in a 512K EEPROM memory chip with a die size of 4.3 mm. by 7 mm.

Special issue on Ambient Intelligence

Ambient Intelligence (AmI) refers to predominantly electronic solutions that allow environments to be sensitive, adaptive, and responsive to the presence of people (Aarts et al. 2002). This opens up a world of unprecedented experiences to people in their day to day surroundings. Building on the early ideas of ubiquitous computing by Marc Weiser (1991) who envisioned a digital world where electronic devices are embedded to form a fine grained distributed network, AmI aims to go further in integration by involving the entire environment and any physical object in the interaction with people, thus improving their well being, productivity, creativity, and leisure through enhanced user system interaction. Furthermore, beyond mere physical integration of electronics, this paradigm focuses on the creation of enhanced experiences, thereby having major cultural and business related implications (Aarts and Encarnacao 2006; Aarts and Marzano 2003). The notion ambience in Ambient Intelligence refers to the need for a large-scale embedding of technology in a way that it becomes unobtrusively integrated into every-day objects and environments. The notion intelligence reflects that the digital surroundings exhibit specific forms of social interaction, i.e., the environments should be able to recognize the people that live in it, personalize to individual preferences, adapt themselves to the users, learn from their behavior, and possibly act upon their behalf. This implies that embedding through miniaturization is the main systems design objective from a hardware point of view. From a software point of view we distinguish between the following major AmI functionalities, i.e., context awareness, ubiquitous access, and natural interaction. The user benefits of the AmI paradigm are aimed at improving the quality of peoples’ lives by creating the desired atmosphere and functionality via intelligent, personalized, interconnected systems and services. However simple this requirement may sound, its true realization is for the time being not within our reach. There are three global factors that enable the development of Ambient Intelligence, i.e., technology, global connectivity, and socio-economical aspects. Focusing on the technological factor, we use a well-known frame of reference provided by the developments in semiconductor industry, which is known as Moore’s law (Noyce 1977). This law states that the integration density of systems on silicon doubles every 18 months. This trend is going on for more than 30 years and provides a clear forecast for the development of semiconductor technology. Recently, some new angles have been opened which in conjunction with Moore’s law can be formulated as follows.

The effects of SIPOS passivation on DC and switching performance of high voltage MOS transistors

For long term stability of high voltage NMOS transistors the application of a SIPOS passivation layer over the drift regions has been studied. This has been found to change the device characteristics both for steady state and switching. This paper describes the mechanism of interaction of the SIPOS layer and the drift region of the device and presents 2-dimensional simulation results together with experimental data. An analytical 1-dimensional model is outlined and shown to agree well with the 2-dimensional simulation results.

TEFET-a high density, low erase voltage, trench flash EEPROM

A novel three-dimensional flash EEPROM cell named the TEFET (Trench Embedded Field Enhanced Tunneling) has been developed for ultra high density memory applications. The cell technology is compatible with standard CMOS processes. It provides very small cell size, large read current, low erase voltage, greatly improved cycling endurance, and excellent scalability as compared to conventional planar cells.<<ETX>>

Analysis and characterization of the segmented anode LIGBT

A LIGBT (lateral insulated gate bipolar transistor) structure, called the segmented-anode LIGBT, is presented and analyzed. The anode structure responsible for the injection of minority carriers for conductivity modulation is implemented using segments of p/sup +/ and n/sup +/ diffusion along the device width. This minimizes the forward bias of the p/sup +/ injector during device turn-off, resulting in higher switching speed compared to the shorted-anode LIGBT. Since the n/sup +/ region required for electron extraction is implemented along the device width and consumes only a small amount of area, a reduction in device size is also achieved. The switching speed and reduced device size result in better tradeoff between on-resistance and turn-off time compared with other LIGBTs. Two-dimensional numerical simulations are carried out to demonstrate the operation and characteristics of the structure, and the experimental inductive and resistive switching characteristics of the structure are discussed. >

LDMOS and LIGT's in CMOS technology for power integrated circuits

In MOS Power Integrated Circuits, the Lateral Double Diffused MOS Transistor (LDMOS) has been used as a power device because of its ease of integration with CMOS circuitry. In this paper, two versions of a Switched Mode Power Supply chip are described using Lateral Insulated Gate Transistor (LIGT) in one and LDMOS in the other. The LIGT version results in substantial reduction of die size for the same functionality because of the reduced specific on-resistance of the LIGT in comparison with LDMOS. An-type epitaxial layer process and RESURF concept has been used to implement the two high voltage designs with CMOS control circuitry.

Opportunities and challenges with net zero energy buildings

Buildings represent around 41% of the total energy consumption in the US followed closely by industry (31%) and transportation (28%). One of the milestones set by the US Department of Energy is the development and deployment of net zero energy buildings defined as buildings that on a yearly average spend as much energy as they generate using renewable energy sources. Realization of net zero energy buildings require a wide ranges of technologies, systems and solutions with varying degrees of complexity and sophistication depending upon the location and surrounding environmental conditions. Lighting is a dominant load in buildings followed by heating, cooling, ventilation and various plug loads. This paper will address the roles of different technologies, devices and control strategies being developed for low energy buildings leading to net zero energy buildings. These include high efficiency lighting, daylight integration, DC power bus, solar power integration; closed loop integrated control, smart grid interface as well as emerging approaches such as chilled beams and active facades. All of these involve power conversion and controls in one form or the other where high voltage or high power integrated solutions are key to commercial viability. In addition to this, the role of whole building modeling and simulation in the development and deployment of the solutions will be addressed.

High-breakdown-voltage devices in ultra-thin SOI

The possible advantages of an SOI (silicon-on-insulator) RESURF (reduced surface electric field) device are explored with an idealized lateral diode structure consisting of a P/sup +/ diffusion into an N-silicon-on-insulator film, supported by an N/sup +/ silicon substrate. An optimized structure is shown to have a uniform lateral electric field and a vanishing vertical electric field along the top surface of the depletion region. An analytical model based on ionization integrals indicates that, for very thin SOI, the breakdown voltage increases with decreasing SOI thickness. Two-dimensional numerical breakdown simulations also support this finding. Experimentally, breakdown voltages in excess of 700 V have been demonstrated on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers, in excellent agreement with theory. An obvious advantage of this concept lies in the integration of high-voltage devices with high-performance SOI CMOS circuits on a single chip.<<ETX>>

Nonuniform and latchup current detection in lateral conductivity modulated FETs

Three-dimensional effects on current distribution in lateral conductivity modulated power transistors such as the lateral insulated-gate bipolar transistor (LIGBT) are studied using the infrared microscopy technique. Nonuniform current distribution and the location of the latchup sites in these devices have been identified. This provides experimental insights into the design and optimization of these high-voltage power transistors. For optimized p/sup +/ anode LIGBT devices with a breakdown voltage of 600 V, a current density of 200 A/cm/sup 2/ at a forward voltage of 2 V, which is comparable to the DMOS IGBT, and a latchup current density above 800 A/cm/sup 2/ have been obtained.<<ETX>>