Theodore Letavic

Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors

The dependence of avalanche breakdown voltage on the drift region length and buried oxide thickness of thin silicon-on-insulator (SOI) LDMOS transistors is reported. An ideal relationship between breakdown voltage and drift length is derived. Experimental SOI LDMOS transistors with near ideal breakdown voltages in the short-drift-length regime have been realized. Specifically, 380 V was achieved in a drift length of 20 mu m. Thin buried oxides are shown to be a major cause of deviation from this ideal. Experimental results verify this finding. An 860-V LDMOS transistor made in a 0.2 mu m-thick SOI layer is reported.<<ETX>>

High performance 600 V smart power technology based on thin layer silicon-on-insulator

A high-performance 600 V smart power technology has been developed in which novel lateral double-diffused MOS transistors (LDMOS) are merged with a BiCMOS process flow for the construction of power integrated circuits on bonded silicon-on-insulator (BSOI) substrates. All active and passive device structures have been optimized for fabrication on BSOI layers which are less than 1.5 /spl mu/m-thick, with buried oxide layers in the range of 2.0 to 3.0 /spl mu/m-thick. Complete dielectric isolation processing is straightforward due to the use of a thin SOI active device layer. A dual field plate design of the high-voltage devices results in at least a factor-of-two reduction in specific on-resistance over conventional LDMOS structures for a given breakdown voltage.

Lateral smart-discrete process and devices based on thin-layer silicon-on-insulator

A ten-mask lateral smart-discrete process technology which combines novel high-voltage RESURF transistor structures and a merged bipolar/DMOS process flow on thin-layer SOI substrates is presented. Benchmarking shows that 650 V/1.2 Ohm SOI lateral smart-discrete devices exhibit a total gate charge which is a factor-of-two lower than vertical super-junction devices, a temperature-independent body diode reverse recovery time which is a factor-of-two smaller than vertical ultra-fast silicon diodes, and total hard-switching losses which are lower than conventional VDMOS. The total gate charge, reverse recovery time, and switching delay times are the lowest reported values for 650 V silicon devices. This, in conjunction with a process with integrated logic, establishes SOI smart-discrete technology as best-in-class for efficient high-frequency power conversion.

650V SOI LIGBT for Switch-Mode Power Supply Application

This paper presents a thin-layer high voltage silicon-on-insulator conductivity modulated device which has been optimized for use within integrated switch mode power supply applications. The device contains a linearly-graded charge profile in the drift region, and the fast-switching LIGBT can be used at current densities which are at least a factor-of-two greater than the SOI LDMOS of equivalent breakdown voltage (LIGBT BVds 650V/Rsp 4 ohm mm2). A device failure mechanism which occurs during shorted-winding SMPS transients unique to thin-layer devices has been documented, and device protection circuitry has been developed to provide a transient current limit mechanism within the high voltage device. The electrical characteristics of the protected conductivity modulated thin-layer SOI high voltage device are comparable to state-of-the-art discrete components, and as such this process technology provides a monolithic alternative for miniaturization and integration of switch mode power supply topologies

High-temperature performance of SOI and bulk-silicon RESURF LDMOS transistors

High-temperature off-state and on-state characteristics of bulk-Si and thin-SOI RESURF LDMOS transistors were studied experimentally and theoretically. The off-state leakage current in the SOI devices was only 1.5 nA//spl mu/m at 300/spl deg/C. The increase of on-resistance with temperature in the SOI devices is smaller than in the bulk-Si devices because of the heavier doping dictated by the RESURF principle. The reverse recovery time of the SOI device shows only slight temperature dependence. The results of this study indicate that LDMOS transistors fabricated in thin SOI layers are well suited for high-temperature power IC applications.

Evaluation of wafer bonding and etch back for SOI technology

Abstract Film quality and crystalline perfection of SOI layers obtained by bonding and etch back silicon-on-insulator (BESOI) technology have been studied. In particular, the various mechanisms of defect generation that contribute to a degradation of the original bulk Si quality in the superficial Si layer of such SOI structures have been investigated. Utilizing transmission x-ray topography combined with transmission electron microscopy (TEM), the critical processing parameters causing defect generation have been identified and the principal mechanisms of dislocation nucleation have been elucidated. Strain compensated bonded SOI wafers have also been evaluated by non-destructive elastic light scattering and optical beam induced current (OBIC) to obtain topographic defect maps of entire SOI wafers. This analytical technique has the capability to comprehensively characterize surface and subsurface morphological features which result from the bonding and thinning processing steps. A comparison of wafer bonding and etch back technology with different etch stop fabrication techniques is presented. In this review, it is demonstrated that the presence of a boron-doped etch stop layer, with its accompanying lattice contraction and strain compensation, represents a key difference in the observed morphological patterns of bonded SOI wafers.

600 V power conversion system-on-a-chip based on thin layer silicon-on-insulator

An integrated 600 V power conversion system is described based on smart power technology which combines novel lateral high-voltage RESURF transistor structures and a merged bipolar/CMOS/DMOS process flow on thin-layer SOI substrates. A new high-voltage SOI LDMOS device structure is presented which results in a factor-of-two decrease in specific on-resistance and a factor-of-two improvement in source-follower saturated current, thus overcoming a key limitation of integrated thin-layer technology. This opens new application areas for thin-layer SOI, such as lighting electronics, power modules, motor control, and others, a significant development for the integration of power conversion systems.

Thin-layer silicon-on-insulator high-voltage PMOS device and application

We present a thin-layer silicon-on-insulator (SOI) high-voltage PMOS device structure and measured performance characteristics. The all-implanted device structure supports voltage by multi-dimensional depletion from a combination of implanted surface pn junctions and MOS capacitor structures formed with multi-level dielectric deposition and metallization. A graded-doped body region has been optimized for application voltages from 100-600 V, and the structure has been evaluated in applications including high-voltage level shifting, low-dissipation bias networks, and high-voltage high-frequency class AB power output stages. The integrated high-voltage PMOS device structure enables low-power, high voltage, and high-speed complementary circuit topologies to be realized in a thin-layer SOI process flow, improving circuit efficiency and expanding the application base for thin-layer technology.

High-temperature off-state characteristics of thin-SOI power devices

High-temperature off-state characteristics of thin-SOI RESURF LDMOS transistors were studied experimentally and theoretically and compared with off-state characteristics of junction-isolated bulk-Si power devices. At 200/spl deg/C, the off-state leakage current in the SOI devices was approximately 200 times lower than in the bulk-Si devices with a comparable breakdown voltage and on-resistance. At 300/spl deg/C, well beyond the operating range of the bulk devices, the off-state leakage current in the SOI devices was only 1.5 nA//spl mu/m. The leakage current appears to scale with the thickness of the SOI layer. The results of this study indicate that LDMOS transistors fabricated in thin SOI layers are well suited for high-temperature power IC applications.

EVALUATION OF STRAIN SOURCES IN BOND AND ETCHBACK SILICON-ON-INSULATOR

Abstract The incorporation of strain is inherent in the manufacture of bond and etchback silicon-on-insulator (BESOI) substrates. In this paper, the principal sources of strain are identified and the magnitude of the strain is estimated. The strain sources discussed include dopant (boron) induced lattice contraction of the etchstop layer, differential thermal expansion, and interfacial microroughness at the time of bonding. Reduction or elimination of SOI layer degradation from some of these strain sources is possible.