Emil Arnold

Realization of high breakdown voltage (>700 V) in thin SOI devices

The avalanche breakdown voltage of silicon on insulator (SOI) lateral diodes is investigated theoretically and experimentally. Theoretically, a condition is derived for achieving a uniform lateral electric field and thus optimizing the breakdown voltage. Using this condition, it is shown that, for SOI thicknesses below about 1 mu m, diode breakdown voltage increases with decreasing SOI layer thickness. Experimentally, breakdown voltages in excess of 700 V have been demonstrated for the first time on diodes having approximately 0.1- mu m-thick SOI layers and 2- mu m-thick buried oxide layers. The results obtained demonstrate the feasibility of making high-voltage thin-film SOI LDMOS transistors and, more importantly, the ability to integrate such devices with high-performance ultra-thin SOI CMOS circuits on a single chip.<<ETX>>

Effect of interface states on electron transport in 4H-SiC inversion layers

The effect of trapping in interface states on channel conductance and field-effect mobility in SiC MOSFETs is studied experimentally and theoretically. Hall effect measurements in n-channel MOS devices with varying densities of interface states were used to determine the effect of trapping on carrier mobility. The dependence of electron mobility on immobile interfacial charge density was quantified and was found to be similar to that in silicon, provided that the mobility is normalized to /spl mu//sub 0/, the value in the absence of Coulomb scattering. A relationship has been established between the ratio of field-effect mobility to the actual carrier mobility and the density of interface states at the Fermi energy.

Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistors

The dependence of avalanche breakdown voltage on the drift region length and buried oxide thickness of thin silicon-on-insulator (SOI) LDMOS transistors is reported. An ideal relationship between breakdown voltage and drift length is derived. Experimental SOI LDMOS transistors with near ideal breakdown voltages in the short-drift-length regime have been realized. Specifically, 380 V was achieved in a drift length of 20 mu m. Thin buried oxides are shown to be a major cause of deviation from this ideal. Experimental results verify this finding. An 860-V LDMOS transistor made in a 0.2 mu m-thick SOI layer is reported.<<ETX>>

High performance 600 V smart power technology based on thin layer silicon-on-insulator

A high-performance 600 V smart power technology has been developed in which novel lateral double-diffused MOS transistors (LDMOS) are merged with a BiCMOS process flow for the construction of power integrated circuits on bonded silicon-on-insulator (BSOI) substrates. All active and passive device structures have been optimized for fabrication on BSOI layers which are less than 1.5 /spl mu/m-thick, with buried oxide layers in the range of 2.0 to 3.0 /spl mu/m-thick. Complete dielectric isolation processing is straightforward due to the use of a thin SOI active device layer. A dual field plate design of the high-voltage devices results in at least a factor-of-two reduction in specific on-resistance over conventional LDMOS structures for a given breakdown voltage.

Electrical conductivity of semi‐insulating polycrystalline silicon and its dependence upon oxygen content

An explanation is given for the strong dependence of electrical conductivity of semi‐insulating polycrystalline silicon films on oxygen content. The proposed model assumes a shell structure such that each Si grain is surrounded by a layer of SiO2, the thickness of which is related to the oxygen content of the film. The conduction proceeds by tunneling of thermally generated carriers through the oxide layers separating adjacent grains. The model properly predicts the dependence of the low‐field conductivity on both oxygen concentration and temperature without any adjustable parameters. Evidence for oxide barrier lowering for barrier thicknesses <5 A is observed.

Disorder‐induced carrier localization in silicon surface inversion layers

Potential fluctuations in silicon surface inversion layers give rise to carrier localization in this quasi‐two‐dimensional system. A semiclassical model is used to evaluate the density of states in the tails below the bands of extended states. To investigate the carrier transport in the tails, we have measured the Hall mobility at lower temperatures and carrier concentrations than has previously been reported. The observed results cannot be accounted for by thermal excitation to extended states above a mobility gap or by thermally activated hopping in localized states. An explanation based on percolation theory is suggested.

Charge-sheet model for silicon carbide inversion layers

The charge-sheet model for metal-oxide-semiconductor (MOS) inversion layers is extended to silicon carbide. The generalized model is based on an analytical solution of the Poisson equation for the case of incomplete ionization of dopant impurities and incorporating Fermi-Dirac statistics. The results are compared with the conventional charge-sheet model which assumes complete impurity ionization and nondegenerate statistics. It is found that, at room temperature and for gate voltages in weak and moderate inversion, the present model predicts higher inversion-layer charge density at a given gate voltage. However, the relationship between the inversion charge and the surface Fermi potential is essentially independent of the degree of impurity ionization. In strong inversion or at temperatures above /spl sim/600 K, the differences between the two models are small. A formula is given for the threshold voltage as a function of the impurity ionization energy. The effects of several different interface state energy distributions on inversion charge are investigated. It is found that a slowly-varying interface-state density has an effect on threshold voltage of a MOSFET similar to that of a fixed oxide charge, while an interface-state density that increases at least exponentially with energy has the effect of lowering the field-effect mobility and transconductance.

Comparison of self-heating effects in bulk-silicon and SOI high-voltage devices

A study of the self-heating effect in SOI and bulk-Si power devices which were subjected to large transient power overloads is described. The time-dependent temperature rise and decay was measured and compared in the two device types by relating the transient on-resistance of the device to its temperature. The temperature rise in SOI devices is shown to be more rapid than in bulk-Si devices in the initial stage of the power pulse. With extended pulse duration the difference between the temperature rise in SOI and bulk-Si devices converges to a constant value which is proportional to the thickness of the buried oxide. This difference is relatively small in comparison to the overall temperature rise.<<ETX>>

EFFECT OF SURFACE STATES ON ELECTRON MOBILITY IN SILICON SURFACE‐INVERSION LAYERS

DC channel conductance of a number of experimental MOS transistor structures was measured and results used to calculate the surface state density and field‐effect mobility. The mobility was found to increase with decreasing surface state concentration and to approach bulk mobility in samples with the lowest number of surface states. This behavior is shown to be consistent with Coulomb scattering by electrons trapped in surface states.

Conduction mechanisms in bandtails at the SiSiO2 interface

Abstract Hall effect and conductivity data are analysed to elucidate the conduction mechanisms in the bandtails in silicon surface-inversion layers. The experimental galvanomagnetic properties are interpreted as a combination of percolation around, scattering from, and thermal emission over random potential barriers. The results indicate that pseudometallic transport extends into the low-energy region inside the bandtail and, simultaneously, the thermally activated conductance persists above the percolation threshold. At low temperatures the contribution due to tunnelling becomes increasingly important. The rms potential fluctuations are found to increase at low carrier density because of reduced screening as the density of states at the Fermi energy decreases.