Savithri Sundareswaran

Statistical delay computation considering spatial correlations

Process variation has become a significant concern for static timing analysis. In this paper, we present a new method for path-based statistical timing analysis. We first propose a method for modeling inter- and intra-die device length variations. Based on this model, we then present an efficient method for computing the total path delay probability distribution using a combination of device length enumeration for inter-die variation and an analytical approach for intra-die variation. We also propose a simple and effective model of spatial correlation of intra-die device length variation. The analysis is then extended to include spatial correlation. We test the proposed methods on paths from an industrial high-performance microprocessor and present comparisons with traditional path analysis which does not distinguish between inter- and intra-die variations. The characteristics of the device length distributions were obtained from measured data of 8 test chips with a total of 17688 device length measurements. Spatial correlation data was also obtained from these measurements. We demonstrate the accuracy of the proposed approach by comparing our results with Monte-Carlo simulation.

Vectorless Analysis of Supply Noise Induced Delay Variation

The impact of power supply integrity on a design has become acritical issue, not only for functional verification, but also for performanceverification. Traditional analysis has typically applied a worstcase voltage drop at all points along a circuit path which leads to avery conservative analysis. We also show that in certain cases, thetraditional analysis can be optimistic, since it ignores the possibilityof voltage shifts between driver and receiver gates. In this paper, wepropose a new analysis approach for computing the maximum pathdelay under power supply fluctuations. Our analysis is based on theuse of superposition, both spatially across different circuit blocks,and temporally in time. We first present an accurate model of pathdelay variations under supply drops, considering both the effect oflocal supply reduction at individual gates and voltage shifts betweendriver/receiver pairs. We then formulate the path delay maximizationproblem as a constrained linear optimization problem, consideringthe effect of both IR drop and LdI/dt drops. We show how correlationsbetween currents of different circuit blocks can be incorporatedin this formulation using linear constraints. The proposed methodswere implemented and tested on benchmark circuits, including anindustrial power supply grid and we demonstrate a significantimprovement in the worst-case path delay increase.

A stochastic approach to power grid analysis

Power supply integrity analysis is critical in modern high perfor-mance designs. In this paper, we propose a stochastic approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the power grid by the blocks in a design are modelled as stochastic processes and their statistical information is extracted, including correlation infor-mation between blocks in both space and time. We then propose a method to propagate the statistical parameters of the block currents through the linear model of the power grid to obtain the mean and standard deviation of the voltage drops at any node in the grid. We show that the run time is linear with the length of the current wave-forms allowing for extensive vectors, up to millions of cycles, to be analyzed. We implemented the approach on a number of grids, including a grid from an industrial microprocessor and demonstrate its accuracy and efficiency. The proposed statistical analysis can be use to determine which portions of the grid are most likely to fail as well as to provide information for other analyses, such as statistical timing analysis.

Electrical impact of line-edge roughness on sub-45-nm node standard cells

Since line-end roughness (LER) has been reported to be of the order of several nanometers and to not decrease as the device shrinks, it has evolved as a critical problem in sub-45-nm devices and may lead to serious device parameter fluctuations and performance limitations for future very large scale integration (VLSI) circuit applications. We present a new cell characterization methodology that uses the nonrectangular gate print images generated by lithography and etch simulations with the random LER variation. We systematically analyze the random LER by taking the impact on circuit performance due to LER variation into consideration. We observed that the saturation current, delay, and leakage current are highly affected by LER as the gate length becomes thinner. Results show that when the root mean square value of LER is 6 nm from its nominal line edge, the worst case saturation current, delay, and leakage current degradation are as much as 10.3% decrease, 12.4% increase, and 7× increase at a 45-nm-node standard cell. Meanwhile the current, delay, and leakage current degradation at a 32-nm-node cell are up to 19.0% decrease, 21.8% increase, and 4600× increase, respectively.

Optimal placement of power supply pads and pins

Power-distribution networks of very large-scale integrated (VLSI) chips should be designed carefully to ensure reliable performance. A sound power network requires an adequate number of power-supply input connections (pads and pins). Placing them at the best vantage locations helps to reduce the number of supply connections necessary for obtaining quality power distribution. This paper addresses the problem of finding an optimum set of pads, pins, and on-chip voltage regulators, and their placement in a given power-supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads, pins, and regulators. The problem is modeled as a mixed-integer linear program (MILP) with the help of macromodeling techniques. Two new heuristics, in addition to the commonly used branch-and-bound technique, are proposed to make the problem tractable. The effectiveness of the proposed technique is demonstrated on several real chips and memories used in low-power and high-performance applications.

A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming

We propose a novel and efficient charge-based decoupling capacitance budgeting algorithm. Our method uses the macro-modeling technique and effective radius of decoupling capacitance to reduce the size of the problem. We formulate the nonlinear optimization into a linear program (LP) by integrating the nodal equations across a time period of interest and through certain approximations. To reduce the error caused by linearization, we do multiple iterations of the linear program. Experimental results demonstrate that, with the proposed algorithm, even very large power networks (eg. 5 million nodes) can be optimized in a couple of hours with 1-2 transient analyses. Comparison of our algorithm with another heuristic method shows area efficiency and run time advantage of our method

Analyzing the risk of timing modeling based on path delay tests.

As technology scales, it is becoming increasingly difficult for simulation and timing models to accurately predict silicon timing behavior. When a collection of chips fail in timing in a similar way, diagnosis and silicon debug look to find the root-causes for the failure. However, little work has been done to develop a methodology that looks for useful design information in the good-chip data. This paper describes a path-based methodology that correlates measured path delays from the good chips, to the path delays predicted by timing analysis. We explain how to utilize this methodology for evaluating the risk of timing modeling.

Total sensitivity based dfm optimization of standard library cells

Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the overall circuit performance and yield. In this paper we propose a comprehensive sensitivity metric which seamlessly incorporates effects from device criticality, lithographic proximity, and process variations. We develop first-order models to compute these sensitivities, and perform robust layout optimization by minimizing the total delay sensitivity to reduce the delay variation on the nominal process condition and by minimizing the performance gap between the fastest and the slowest delay corners to reduce the leakage current on the process corner. The results on industrial 45nm node standard cells show up to 76% improvement in non-rectangular delay variation under nominal process condition, 24% reduction in the delay difference between the fastest and slowest process corners, and up to 90% reduction in leakage current at the fastest process corner.

Electrical impact of line-edge roughness on sub-45nm node standard cell

As the transistors are scaled down, undesirable performance mismatch in identically designed transistors increases and hence causes greater impact on circuit performance and yield. Since Line-End Roughness (LER) has been reported to be in the order of several nanometers and not to decrease as the device shrinks, it has evolved as a critical problem in the sub-45nm devices and may lead to serious device parameter fluctuations and performance limitation for the future VLSI circuit application. Although LER is a kind of random variation, it is undesirable and has to be analyzed because it causes the device to fluctuate. In this paper, we present a new cell characterization methodology which uses the non-rectangular gate print-images generated by lithography and etch simulations with the random LER variation to estimate the device performance of a sub-45nm design. The physics based TCAD simulation tool is used for validating the accuracy of our LER model. We systematically analyze the random LER by taking the impact on circuit performance due to LER variation into consideration and suggest the maximum tolerance of LER to minimize the performance degradation. We observed that the driving current is highly affected by LER as the gate length becomes thinner. We performed lithography simulations using 45nm process window to examine the LER impact of the state-of-the-art industrial devices. Results show that the rms value of LER is as much as 10% from its nominal line edge, and the saturation current can vary by as much as 10% in our 2-input NAND cell.

Impact of low-impedance substrate on power supply integrity

Although it is tempting to think of the power grid as an independent medium of the transfer of energy from the package to the devices in the IC, some second-order technology-related effects can sometimes cause unforeseen problems. This article focuses especially on the relationship of the power delivery system to the silicon substrate properties, and shows how a low-impendance substrate can make a substantial difference in the noise generated by the power grid.