Sayantan Das

Synthesis of System Verilog Assertions

In recent years, assertion-based verification is being widely accepted as a key technology in the pre-silicon validation of system-on-chip (SOC) designs. The System Verilog language integrates the specification of assertions with the hardware description. In this paper we show that there are several compelling reasons for synthesizing assertions in hardware, and present an approach for synthesizing System Verilog assertions (SVA) in hardware. Our method investigates the structure of SVA properties and decomposes them into simple communicating parallel hardware units that together act as a monitor for the property. We present a tool that performs this synthesis, and also show that the chip area required by the monitors for a industry standard ABV IP for the ARMAMBA AHB protocol is quite modest

Formal methods for analyzing the completeness of an assertion suite against a high-level fault model

One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design intent. Existing literature on FPV coverage does not solve this problem adequately, since they primarily analyze the coverage of a specification against a given implementation. On the other hand, we consider the task of determining the coverage of a formal specification against a high-level fault model that is independent of any specific implementation. We show that such a coverage analysis discovers behavioral gaps in the specification and prompts the design architect to add more properties to close the behavioral gaps. Our results establish that the coverage analysis task at this level is computationally complex, but it is possible to obtain a conservative estimate of the coverage at low cost.

Design-Intent Coverage—A New Paradigm for Formal Property Verification

It is essential to formally ascertain whether the register-transfer level (RTL) validation effort effectively guarantees the correctness with respect to the designs architectural intent. The designs architectural intent can be expressed in formal properties. However, due to the capacity limitations of formal verification, these architectural properties cannot be directly verified on the RTL. As a result, a set of lower level RTL properties are developed and verified against the RTL modules. In a top-down design approach, the architect would ideally like to formally guarantee the coverage of the architectural intent at the time of creating the specifications for the component RTL modules (that is, before they are passed to the designers for implementation). In this paper, the authors present: 1) a method for checking whether the RTL properties are covering the architectural properties, that is, whether verifying the RTL properties guarantees the correctness of the designs architectural intent; 2) a method to identify which architectural properties are still uncovered, that is, not guaranteed by the RTL properties; and 3) a methodology for representing the gap between the specifications in a legible form

Test generation games from formal specifications

In this paper, we present methods for automatic test generation from formal specifications. These are used to create intelligent test benches that are able to cover corner case behaviors in much less time. We have developed a prototype tool for intelligent test generation within the layered test bench architecture proposed in RVM. We present results on verification IPs of standard bus protocols to show the effectiveness of our approach

Design intent coverage revisited

Design intent coverage is a formal methodology for analyzing the gap between a formal architectural specification of a design and the formal functional specifications of the component RTL blocks of the design. In this article we extend the design intent coverage methodology to hybrid specifications containing both state-machines and formal properties. We demonstrate the benefits of this extension in two domains of considerable recent interest, namely (a) the use of auxiliary state-machines in formal specifications, and (b) the use of modest sized RTL blocks in the design intent coverage analysis.

SAT based solutions for consistency problems in formal property specifications for open systems

Formal property verification is increasingly being adopted by designers for module level validation. The behavior of a module is typically expressed in terms of the behavioral guarantee of the module under assumptions on its environment. Expressing such assume-guarantee properties correctly in a formal language is a nontrivial task and errors in the specification are not uncommon. In this paper we examine the main forms of specification errors for open systems, and present SAT based algorithms for verifying the specification against such errors.

What lies between Design Intent Coverage and Model Checking

Practitioners of formal property verification often work around the capacity limitations of formal verification tools by breaking down properties into smaller properties that can be checked on the sub-modules of the parent module. To support this methodology, we have developed a formal methodology for verifying whether the decomposition is indeed sound and complete, that is, whether verifying the smaller properties on the submodules actually guarantees the original property on the parent module. In practice, however designers do not write properties for all modules and thereby our previous methodology was applicable to selected cases only. In this paper we present new formal methods that allow us to handle RTL blocks in the analysis. We believe that the new approach will significantly widen the scope of the methodology, thereby enabling the validation engineer to handle much larger designs than admitted by existing formal verification tools

Formal verification coverage: are the RTL-properties covering the design's architectural intent?

It is essential to formally ascertain whether the RTL validation effort effectively guarantees the correctness with respect to the designs architectural intent. The designs architectural intent can be expressed in formal properties. However, due to the capacity limitation of formal verification, these architectural-properties cannot be directly verified on the RTL. As a result, a set of lower level RTL-properties are developed and verified against the RTL. In this paper we present: (1) a method for checking whether the RTL-properties are covering the architectural-properties, that is, whether verifying the RTL-properties guarantee the correctness of the designs architectural intent; and (2) a method to identify the coverage holes in terms of the architectural properties (or their sub-properties) that are not covered.

A parallel architecture for video compression

This paper reports a parallel algorithm for compression/decompression of video data files. The algorithm can be easily implemented on a parallel pipelined architecture that can support on-line compression/decompression. The hardware implementing the architecture achieves a throughput of 30 frames per second with frame size of 352/spl times/272 pixels.

Architecture of a VLSI chip for modelling amino acid sequence in proteins

A Cellular Automata (CA) based model of amino acids which constitute different types protein is reported in this paper. A simulation engine is being developed based on this model to study protein behaviour.