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Dive into the research topics where Scott A. Bell is active.

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Featured researches published by Scott A. Bell.


Proceedings of SPIE, the International Society for Optical Engineering | 2006

The transfer of photoresist LER through etch

Adam R. Pawloski; Alden Acheta; Scott A. Bell; Bruno La Fontaine; Tom Wallow; Harry J. Levinson

A method is presented to determine a transfer function for line edge roughness (LER) from the photoresist pattern through the etch process into the underlying material, such as a polysilicon gate. The image fading technique was employed to determine the dependence of photoresist LER on the image-log-slope (ILS) of the aerial image. From this initial condition in resist, LER after the etch process was measured in polysilicon and related to the ILS used to pattern the resist. From these two relationships, a transfer function could be derived to quantify the magnitude of LER that transfers into the polysilicon under layer from the photoresist. A gate layer type film stack and a 193nm resist system were employed. Results demonstrated that photoresist LER did transfer through the etch process. Increasing the resist LER increased the post-etch LER in polysilicon, and accordingly, minimizing resist LER minimized polysilicon LER. The etch process can reduce the magnitude of roughness in polysilicon over a range of mid and low spatial frequencies, however the extent of the roughness reduction diminishes as the resist LER reaches its minimum at large values of the ILS. In addition, resist trim rates during etch were apparently increased when LER of the resist was large. These results demonstrate that post-etch LER in polysilicon may be limited by the minimum LER achievable in resist, despite the occurrence of apparent smoothing mechanisms through the etch process.


Archive | 1999

Process for fabricating a semiconductor device component using a selective silicidation reaction

Qi Xiang; Scott A. Bell; Chih-Yuh Yang


Archive | 2003

Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning

Philip A. Fisher; Marina V. Plat; Chih-Yuh Yang; Christopher F. Lyons; Scott A. Bell; Douglas J. Bonser; Lu You; Srikanteswara Dakshina-Murthy


Archive | 2002

Method of forming sub-lithographic spaces between polysilicon lines

Scott A. Bell; Philip A. Fisher; Richard C. Nguyen; Cyrus E. Tabery


Archive | 2001

Bi-layer trim etch process to form integrated circuit gate structures

Marina V. Plat; Scott A. Bell; Christopher F. Lyons; Ramkumar Subramanian; Bhanwar Singh


Archive | 2000

Method using a thin resist mask for dual damascene stop layer etch

Fei Wang; Christopher F. Lyons; Khanh B. Nguyen; Scott A. Bell; Harry J. Levinson; Chih Yuh Yang


Archive | 2001

Use of silicon containing imaging layer to define sub-resolution gate structures

Marina V. Plat; Scott A. Bell; Christopher F. Lyons; Ramkumar Subramanian; Bhanwar Singh


Archive | 2001

RELACS process to double the frequency or pitch of small feature formation

Ramkumar Subramanian; Bhanwar Singh; Marina V. Plat; Christopher F. Lyons; Scott A. Bell


Archive | 1998

Thin resist with nitride hard mask for gate etch application

Scott A. Bell; Christopher F. Lyons; Harry J. Levinson; Khanh B. Nguyen; Fei Wang; Chih Yuh Yang


Archive | 1998

Ultra-thin resist and SiON/oxide hard mask for metal etch

Fei Wang; Christopher F. Lyons; Khanh B. Nguyen; Scott A. Bell; Harry J. Levinson; Chih Yuh Yang

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Fei Wang

Advanced Micro Devices

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