Chih-Yuh Yang

Replacement metal-gate NMOSFETs with ALD TaN/EP-Cu, PVD Ta, and PVD TaN electrode

This work reports the first replacement (damascene) metal gate NMOSFETs with atomic layer deposition (ALD) TaN/PVD and electroplated Cu as the stacked gate electrode. Transistors with PVD TaN and PVD Ta electrode are also fabricated. Our data show that ALD TaN has the right work function for the N-MOSFETs. The Cu damascene process can reduce the gate resistivity. The ALD process has the advantage of reducing the stress and radiation damage to the gate oxide. The damascene process flow bypasses high temperature steps (>600/spl deg/C)-critical for metal gate and high-k materials.

Self-aligned nickel, cobalt/tantalum nitride stacked-gate pMOSFETs fabricated with a low temperature process after metal electrode deposition

This letter reports the first replacement (Damascene) metal gate pMOSFETs fabricated with Ni/TaN, Co/TaN stacked electrode, where Ni or Co is in direct contact with the gate SiO/sub 2/, to adjust the electrode metal work function and TaN is used as the filling material for the gate electrode to avoid wet etching and CMP problems. The process is similar to the fabrication of traditional self-aligned polysilicon gate MOSFETs, except that in the back end (after the source/drain implants are activated) a few processing steps are added to replace the polysilicon with metal. Our data show that the Ni or Co/TaN gate electrode has the right work function for the pMOSFETs. The metal gate process can reduce the gate resistivity. Thermal stability of the stacked electrodes is studied and the result is reported in this paper. The damascene process flow bypasses high temperature steps (> 400/spl deg/C)critical for metal gate and hi k materials. This paper demonstrates that a low temperature anneal (300/spl deg/C) can improve the device performance. In this paper, the gate dielectrics is SiO/sub 2/.