Harry J. Levinson

Self-aligned double patterning (SADP) compliant design flow

Double patterning with 193nm optical lithography is inevitable for technology scaling before EUV is ready. In general, there are two major double patterning techniques (DPT): Litho-Etch-Litho-Etch (LELE) and sidewall spacer technology, a Self-Aligned Double Patterning technique (SADP). So far LELE is much more mature than SADP in terms of process development and design flow implementation. However, SADP has stronger scaling potential than LELE due to its smaller design rules on tip-tip and tip-side as well as its intrinsic self-align property. In this paper, we will explain in detail about how to enable a SADP-friendly design flow from multiple perspectives: design constructs, design rules, standard cell library and routing. In addition, the differences between SADP and LELE in terms of design, scaling capability and RC performance will be addressed.

Decomposition strategies for self-aligned double patterning

Spacer technology, a self-aligned double patterning (SADP) technique, has been drawing more and more attention due to its less stringent overlay requirements compared to other double-patterning methods. However, use of SADP techniques was previously limited by the lack of flexibility in terms of decomposition options , and significant developments were mainly implemented for 1D-type applications for memory. In this paper, we extend the SADP technique into the logic field. A matrix of design rule extraction structures was created by GLOBALFOUNDRIES, which was then decomposed into 2-mask SADP patterning solutions by Cadence Design Systems, and wafers were manufactured by Applied Materials. The wafers were processed in both positive and negative spacer tones, and then we evaluate the design capabilities of SADP for logic BEOL patterning on pitches from 56nm to 64nm. It shows that the SADP has big advantage over other pitch splitting techniques such as LELE in terms of design rules, overlay, and CD uniformity control. With SADP, the most challenging design rules for BEOL such as tip-to-tip and tip-to-line can be reduced 50% from 80 nm to 40 nm.

Extreme ultraviolet lithography's path to manufacturing

The origins of extreme ultraviolet (EUV) lithography and its progress toward readiness for manufacturing are recounted. Source power and reliability and mask defects are known items requiring additional improvement before EUV lithography will be suitable for use in the volume manufacturing of integrated circuits. Additional cycles of learning, as obtained from pilot line operation, will greatly accelerate the maturation of EUV lithography and enable its use in manufacturing as early as 2013.

Considerations in Source-Mask Optimization for Logic Applications

In the low k1 regime, optical lithography can be extended further to its limits by advanced computational lithography technologies such as Source-Mask Optimization (SMO) without applying costly double patterning techniques. By cooptimizing the source and mask together and utilizing new capabilities of the advanced source and mask manufacturing, SMO promises to deliver the desired scaling with reasonable lithography performance. This paper analyzes the important considerations when applying the SMO approach to global source optimization in random logic applications. SMO needs to use realistic and practical cost functions and model the lithography process with accurate process data. Through the concept of source point impact factor (SPIF), this study shows how optimization outputs depend on SMO inputs, such as limiting patterns in the optimization. This paper also discusses the modeling requirements of lithography processes in SMO, and it shows how resist blur affect optimization solutions. Using a logic test case as example, the optimized pixelated source is compared with the non-optimized source and other optimized parametric sources in the verification. These results demonstrate the importance of these considerations during optimization in achieving the best possible SMO results which can be applied successfully to the targeted lithography process.

Double patterning compliant logic design

Double patterning technology (DPT) is the only solution to enable the scaling for advanced technology nodes before EUV or any other advanced patterning techniques become available. In general, there are two major double patterning techniques: one is Litho-Etch-Litho-Etch (LELE), and the other is sidewall spacer technology, a Self-Aligned Double Patterning technique (SADP). While numerous papers have previously demonstrated these techniques on wafer process capabilities and processing costs, more study needs to be done in the context of standard cell design flow to enable their applications in mass production. In this paper, we will present the impact of DPT on logic designs, and give a thorough discussion on how to make DPT-compliant constructs, placement and routing using examples with Cadences Encounter Digital Implementation System (EDI System).

DPT restricted design rules for advanced logic applications

Double patterning technology (DPT) provides the extension to immersion lithography before EUV lithography or other alternative lithography technologies are ready for manufacturing. Besides the additional cost due to DPT processes over traditional single patterning process, DPT design restrictions are of concerns for potential additional design costs. This paper analyzes design restrictions introduced by DPT in the form of DPT restricted design rules, which are the interface between design and technology. Both double patterning approaches, Litho-Etch-Litho-Etch (LELE) and Self-Aligned Double Patterning with spacer lithography (SADP), are studied. DPT design rules are summarized based on drawn design layers instead of decomposed layers. It is shown that designs can be made DPT compliant designs if DPT design rules are enforced and DPT coloring check finds no odd cycles. This paper also analyzes DPT design rules in the design rule optimization flow with examples. It is essential to consider DPT design rules in the integrated optimization flow. Only joint optimization in design rules between design, decomposition and process constraints can achieve the best scaled designs for manufacturing. This paper also discusses DPT enablement in the design flow where DPT aware design tools are needed so that final designs can meet all DPT restricted design rules.

Comparative study of line width roughness (LWR) in next-generation lithography (NGL) processes

In this paper, we conduct a comprehensive comparative study of next-generation lithography (NGL) processes in terms of their line width roughness (LWR) performance. We investigate mainstream lithography options such as double patterning lithography (DPL), self-aligned double patterning (SADP), and extreme ultra-violet (EUV), as well as alternatives such as directed self-assembly (DSA) and nano-imprint lithography (NIL). Given the distinctly different processing steps, LWR arises from different sources for these patterning methods, and a unified, universally applicable set of metrics must be chosen for useful comparisons. For each NGL, we evaluate the LWR performance in terms of three descriptors, namely, the variation in RMS amplitude (σ), correlation length (see manuscript) and the roughness exponent (α). The correlation length (which indicates the distance along the edge beyond which any two linewidth measurements can be considered independent) for NGL processes is found to range from 8 to 24 nm. It has been observed that LWR decreases when transferred from resist into the final substrate and all NGL technology options produce < 5% final LWR. We also compare our results with 2008 ITRS roadmap. Additionally, for the first time, spatial frequency transfer characteristics for DSA and SADP are being reported. Based on our study, the roughness exponent (which corresponds to local smoothness) is found to range from ~0.75-0.98; it is close to being ideal (α = 1) for DSA. Lastly using EUV as an example, we show the importance of process optimization as these technologies mature.

22-nm-node technology active-layer patterning for planar transistor devices

As the semiconductor device size shrinks without a concomitant increase of numerical aperture (NA) and refractive index of the immersion fluid, printing 22-nm-technology devices presents challenges in resolution. Therefore, aggressive integration of a resolution enhancement technique (RET), design for manufacturability (DFM), and layer-specific lithographic process development are strongly required in 22-nm-technology lithography. We show patterning of an active layer of a 22-nm-node planar logic transistor device, and discuss achievements and challenges. Key issues identified include printing tight pitches, isolated trench, and 2-D features while maintaining a large lithographic process window across the chip while scaling down the cell size. Utilizing NA=1.2, printing of the static random access memory (SRAM) of a cell size of 0.1 µm2 and other critical features across the chip with a process window are demonstrated.

Modeling and Characterization of Contact-Edge Roughness for Minimizing Design and Manufacturing Variations in 32-nm Node Standard Cell

Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state-of-the-art lithography process; meanwhile, the design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depend on contact area and shape, larger CER results in significant change in a device current. In this paper, we first propose a CER model based on power spectral density function which is a function of RMS edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress induced CMOS cells. Using the results of CER, we analyze the impact of CER variation on the S/D contact resistance and the device saturation current. Results show that when the rms value of CER is 10nm, the S/D contact resistance and the device saturation current can vary by as much as 57.8% and 2.1%, respectively.

Modeling and characterization of contact-edge roughness for minimizing design and manufacturing variations

Despite intensive attention on line-edge roughness (LER), contact-edge roughness (CER) has been relatively less studied. Contact patterning is one of the critical steps in a state of the art lithography process; meanwhile, design rule shrinking leads to larger CER in contact holes. Since source/drain (S/D) contact resistance depends on contact area and shape, larger CER results in significant change in a device current. We first propose a CER model based on the power spectral density function, which is a function of rms edge roughness, correlation length, and fractal dimension. Then, we present a comprehensive contact extraction methodology for analyzing process-induced CER effects on circuit performance. In our new contact extraction model, we first dissect the contact with a same distance, and then calculate the effective resistance considering both the shape weighting factor and the distance weighting factor for stress-induced complementary metal-oxide semiconductor (CMOS) cells. Using the results of CER, we analyze the impact of both random CER and systematic variation on the S/D contact resistance, and the device saturation current. Results show that the S/D contact resistance and the device saturation current can vary by as much as 135.7 and 4.9%, respectively.