Scott Barrett

Ultra CSP/sup TM/-a wafer level package

There has been a significant amount of work over the past five years on chip scale packaging. The majority of this work has been an extension of conventional integrated circuit (IC) packaging technology utilizing either wire bonders or tape automated bonding (TAB)-type packaging technology. Handling discrete devices during the IC packaging for these type of chip scale packages (CSPs) has resulted in a relatively high cost for these packages. This paper reports a true wafer level packaging (WLP) technology called the Ultra CSP/sup TM/. One advantage of this WLP concept is that it uses standard IC processing technology for the majority of the package manufacturing. This makes the Ultra CSP ideal for both insertion at the end of the wafer fab as well as the facilitation of wafer level test and burn-in options. This is especially true for dynamic random access memory (DRAM) wafers. Wafer level burn-in and wafer level processing can be used for DRAM and other devices as a way to both reduce cost and improve cycle time. Thermal cycling results for Ultra CSPs with a variety of package sizes and input/output (I/O) counts are presented. These test vehicles, assembled to FR-4 boards without underfill, cover a range of footprints typical of flash memory, DRAM and other devices. The electrical and thermal performance characteristics of the Ultra CSP package technology are discussed.

Solder joint reliability of a polymer reinforced wafer level package

Abstract Wafer level packages (WLPs) have demonstrated a very clear cost-advantage vs traditional wire-bond technologies, especially for small components that have a high number of dice and I/O per wafer. Ultra CSP® is a WLP developed by the Kulicke & Soffa Flip Chip Division (formally Flip Chip Technologies). Typical products utilizing the Ultra chip scale package (CSP) have 5×5 or less area arrays at 0.5 mm pitch. This relatively small array has been limited by the inherent solder joint reliability of WLPs. A much larger subset of higher I/O IC’s could benefit from WLPs provided that standard reliability requirements are achieved without the use of underfill. A new polymer reinforcement technology, “Polymer Collar WLP™”, has been developed by K&S Flip Chip Division. Polymer Collar WLP utilizes a polymer reinforcement structure surrounding the solder joint and it has demonstrated more than 50% increase in solder joint life in thermal cycling tests. The most attractive feature of the Polymer Collar WLP process is its simplicity. A simple replacement of the standard solder flux with Polymer Collar material during the solder attach process is all that is required. This simplicity makes Polymer Collar the most cost-effective solution for adding a polymer reinforcement structure to the solder joint. Other methods in use today require additional complex and costly manufacturing steps. This Polymer Collar WLP is expected to widen the WLP market to include larger arrays where the Ultra CSP did not have suitable solder joint reliability.

Reliability characterization in Ultra CSP/sup TM/ package development

Ultra CSP/sup TM/ is a wafer-level chip scale package developed by Flip Chip Technologies. This package provides a low cost packaging solution for various applications such as integrated passive, flash memory, DRAM, and Direct RDRAM/sup TM/ devices. This paper presents a brief update of the Ultra CSP development effort. Two design concepts were evolved in the development process and product implementation to address the requirements of different applications. Solder joint reliability of Ultra CSP was evaluated at board level under thermal cycle test. A solder joint fatigue database was generated using Weibull analysis. The effect of die size (DNP), bump standoff, substrate pad size, and solder ball size are discussed. Continued improvement in the package reliability is achieved through Design of Experiments. Issues encountered in the qualification stage are addressed in terms of accelerated test strategy, process quality control, package design, and substrate design.

A new wafer level package for improved electrical and reliability performance

Wafer level packages (WLPs) have demonstrated a very clear size and cost advantage vs. traditional wirebond technologies, especially for small components that have a high number of dice and I/O per wafer. The Kulicke & Soffa Flip Chip Division (FCD) introduced its first WLP in 1998. This initial WLP utilized a bump on nitride structure (BON) which had good reliability but also high input capacitance. A new WLP has been developed by FCD. This new WLP has a solder bump on polymer (BOP) dielectric structure. A major driver for pursuing a BOP structure was to achieve minimal input capacitance for high speed applications. During development, a new polymer dielectric material was carefully selected based on reliability tests and manufacturability. Thermal Cycling (TC) test showed 30% better TC performance vs. the BON structure. The new WLP also passed 168 hours of autoclave and JEDEC Level 1 Preconditioning testing. In this paper, the advantages of this new WLP will be discussed in detail. In addition, reliability test results will be presented.