Scott Charles Warner

Substrate coupling in digital circuits in mixed-signal smart-power systems

This paper describes theoretical and experimental data characterizing the sensitivity of nMOS and CMOS digital circuits to substrate coupling in mixed-signal, smart-power systems. The work presented here focuses on the noise effects created by high-power analog circuits and affecting sensitive digital circuits on the same integrated circuit. The sources and mechanism of the noise behavior of such digital circuits are identified and analyzed. The results are obtained primarily from a set of dedicated test circuits specifically designed, fabricated, and evaluated for this work. The conclusions drawn from the theoretical and experimental analyses are used to develop physical and circuit design techniques to mitigate the substrate noise problems. These results provide insight into the noise immunity of digital circuits with respect to substrate coupling.

Placement of Substrate Contacts to Minimize Substrate Noise in Mixed-Signal Integrated Circuits

The placement of substrate contacts in epi and non-epi technologies is analyzed in order to control and reduce the substrate noise amplitude and spreading. The choice of small or large substrate contacts or rings for each of the two major technologies is highlighted. Design guidelines for placing substrate contacts so as to improve the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.

Physical design to improve the noise immunity of digital circuits in a mixed-signal smart-power system

Theoretical, simulation and experimental analysis and data are presented, discussing physical design techniques which influence the noise behavior of digital circuits in a mixed-signal smart-power system. Several physical design strategies are presented to improve the noise immunity of digital circuits in smart-power systems.

A universal CMOS voltage interface circuit

A CMOS interface circuit to transfer a digital signal between two circuits of different supply voltages is described. The interface can be used, for example, between 3 volt and 5 volt or higher voltage families. The principal characteristics of the interface circuit are: no static power dissipation, high speed, and high speed buffering.

Placement of substrate contacts to alleviate substrate noise in epi and non-epi technologies

The placement of substrate contacts in epi and non-epi technologies in order to control and reduce the substrate noise amplitude and spreading is analyzed. The choice of small or large substrate contacts or rings for each of the two major technologies are highlighted. Design guidelines for placing substrate contacts particularly appropriate to improving the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.

A comparative study of the behavior of NMOS and CMOS digital circuits under substrate noise

A comparative study of the behavior of NMOS and CMOS digital circuits in terms of the ability to tolerate substrate noise is presented. Theoretical and simulation results are confirmed by experimental data gathered from the analysis of NMOS and CMOS test chips. It is shown that while the noise sensitivity of NMOS digital circuits is influenced by a variety of factors, the primary phenomenon responsible for the noise integrity of the CMOS digital circuits is latch-up.