Scott Davidson

Losing control

This column looks back at the days when we had direct, tactile control of our appliances and wonders what impact the loss of this control is having on our childrens interest in engineering. Increased complexity in our work life also leads to our feeling this lack of direct control. Yet, perhaps its a mistake to pine for those days of direct control. Maybe our childrens ability to find and fix a problem by its symptoms will be essential for testing the products of the future.

ITC'99 Benchmark Circuits - Preliminary Results

The goal of this benchmarking effort is to test new DFT techniques on these real designs. Six panelists will present their preliminary results. Mario Konijnenburg of Philips will present full scan test generation results as a baseline, using the DAT test generation system. Raghuram Tupuri will present results from a hierarchical test generator, creating at-speed tests using functional knowledge without the need for scan. Professor J-E Santucci will describe a test generator for design verification tests, using techniques derived from software testing. Professor S . M. Reddy will describe results from two sequential test generators developed at the University of Iowa. Dr. Chouki Aktouf will describe techniques for the insertion of scan at the functional level. Professor Sujit Dey will describe the testabiiity of one of the benchmarks, and some functional BIST approaches.

Open-source hardware

Open-source software has made great strides. You can now buy a machine with an open-source operating system, browser, and office productivity package. Recent reports have recommended users switch to open-source browsers, away from less-secure commercial ones. The market for these products is growing rapidly.

Towards an understanding of no trouble found devices

This paper gives a model for understanding no trouble found (NTF) parts, including predictions of how many can be expected at different stages of a product life cycle, an understanding of when NTFs are of concern, and when they are to be expected. We also show how NTF rates can be used as a measure of process health.

Using transition test to understand timing behavior of logic circuits on UltraSPARC TM T2 family

Delay test is crucial for finding slow paths and slow ICs, both during bringup and during speed binning. Path delay test has traditionally been considered to be superior in finding slow paths. This paper describes our experiments indicating that this is not always the case. For the UltraSPARC T2 microprocessor series we found that transition delay test often ran slower, was more effective in finding the root cause of the slow path, and correlated well with functional diags also used for speed binning. Transition test does a better job finding delay issues related to the impact of simultaneous switching and coupling noise on chip speed. We used transition test to measure the impact on chip timing of voltage, temperature, and we also used it to confirm the results of improving slow paths.

Behavioral Test Economics

This paper raises the issue of why test engineers often do not act in ways which test economics says are optimal. The new field of behavioral economics explains why people often do not act in their economic self interest, and the authors propose that some of the same principles, applied to testing, can explain some of the behavior of test engineers. The authors use several examples to illustrate these principles, and for each describe the underlying economic and behavioral economic principles behind them, and give recommendations for decision makers

Simplified metrics for evaluating designs for testability

Design for Testability (DFT) evaluation is quite complex and circuit dependent. To simplify the analysis and to apply the methodology more generally to different circuit types and different levels of assembly, we focus our efforts on identifying areas of poor testability. We introduce metrics we call Sensitized Path Oriented Testability Scoring ™ or SPOTS ™, performed at all points where failure modes are to be detected and diagnosed, to spot poor testability. Once the problem is identified early in the design stage, especially when it is correlated with a circuit node and a failure mode, the remedy needed to correct the problem through DFT can be quite practical. SPOTS measures four testability attributes - controllability, distinguishability, test resource costs, and test escapes due to lack of testability. The metrics simplify previous testability techniques, by utilizing sensitized paths to measure circuit controllability. The use of sensitized paths greatly reduces the analysis required, and while it may not offer validation of testability, it succeeds in highlighting areas that lack testability. Controllability metric (CM) provides a number corresponding to the number of steps required to sensitize a path. Distinguishability metric (DM) measures the difficulty of isolating one fault from others. Test resource cost (RC), includes test program set (TPS) development costs and test equipment requirements, and is expressed in monetary currency. Penalty cost (PC) measures in currency the cost incurred for nodes left untested by escaping detection in tests. Associating each of these metrics to failure modes at each node creates a table that reveals where testability problems exist. Designers and testability analysts can work together to resolve them either by altering the fault detection and isolation requirements, improving test resources and/or redesigning the unit under test (UUT). This form of analysis is simpler to use and is applicable to any level of assembly — IC, board or system. It can even be utilized by those procuring commercial off the shelf (COTS) products to compare support costs for competing products.

Justifying DFT with a hierarchical top-down cost-benefit model

How can we justify system level DFT? We must show that it has a positive return on investment (ROI). Existing test ROI models are manufacturing centric, do not account for the disaggregation of the product realization process, and are often focused on a specific DFT method. We propose a new, top-down, hierarchical ROI model, which starts with potential benefits and can handle entire systems more effectively than current models.

A framework for testability metrics across hierarchical levels of assembly

We cannot improve what we cannot measure and a major issue with system test today is that we do not know how effective it is in detecting defects, diagnosing failures, and ensuring field quality. This situation is in contrast to that of ICs, where test quality metrics have resulted in DPMs of 100 – 1000 at board and system test and mean time to failures in the hundreds of millions of hours. This paper proposes a framework for system level coverage metrics, using fault sampling and a variety of defect models.

The Psychology of Electronic Test

Test-related decisions have important consequences for product cost, quality, reliability, and information gathering. Yet, the persons making those decisions are - like all of us - imperfect. This article suggests ways to improve our understanding of our own decision making with an eye toward making the best choices possible in the area of electronic test.