Kamran Zarrineh

On programmable memory built-in self test architectures

The design and architectures of a microcode-based memory BIST and programmable FSM-based memory BIST unit are presented. The proposed microcode-based memory BIST unit is more efficient and flexible than existing architectures. Test logic overhead of the proposed programmable versus nonprogrammable memory BIST architectures is evaluated. The proposed programmable memory BIST architectures could be used to test memories in different stages of their fabrication and therefore result in lower overall memory test logic overhead. We show that the proposed microcode-based memory BIST architecture has better extendibility and flexibility while having less test logic overhead than the programmable PSM-based memory BIST architecture.

Design and analysis of multiple weight linear compactors of responses containing unknown values

Occurrence of unknown values in scan chains in response to test vectors is a common phenomenon. This paper presents a method for designing matrices for linear test output compactors by using rows of multiple weights. Compared to previously proposed compactors, the method reduces the masking caused by unknowns by an order of magnitude provided that the unknowns are non-uniformally distributed among the scan chains. Also, using multiple rather than single weight compactors increases the compaction ratio and reduces the hardware overhead. The effectiveness of multiple weight compactors is demonstrated through analysis, simulations and experiments with test response from an industrial design

Programmable memory BIST and a new synthesis framework

The development of two programmable memory BIST architectures is first reported. A memory synthesis framework which can automatically generate, verify and insert programmable as well as non-programmable BIST units is developed as a vehicle to efficiently integrate BIST architectures in todays memory-intensive systems. Custom memory test algorithms could be loaded in the developed programmable BIST unit and therefore any type of memory test algorithm could be realized. The flexibility and efficiency of the framework are demonstrated by showing that these memory BIST units could be generated, functionally verified and inserted in a short time.

A new framework for generating optimal March tests for memory arrays

Given a set of memory array faults the problem of computing an optimal March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory army fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compute the optimal March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented.

Self test architecture for testing complex memory structures

The structural complexity and test challenges of complex dependent memory structures are described. An isolation strategy to minimize the test logic overhead and delay penalty is presented. A set of custom memory test algorithms is designed to test the memory cell, bridging and multi-port faults in complex dependent memory structures. A novel programmable memory BIST architecture to realize the developed custom memory test algorithms has been described. The proposed memory BIST architecture can be used to test the dependent memory structures in different stages of their fabrication and assembly. The experimental results demonstrate the area overhead of different components of the proposed programmable memory BIST architecture.

A new framework for automatic generation, insertion and verification of memory built-in self test units

The design and architecture of a memory test synthesis framework for automatic generation, insertion and verification of memory BIST units is presented. We use a building block architecture which results in full customization of memory BIST units. The flexibility and efficiency of the framework are demonstrated by showing that memory BIST units with different architecture and characteristics could be generated, functionally verified and inserted in a short time. Custom memory test algorithms could be loaded in the supported programmable BIST unit and therefore any type of memory test algorithm could be realized.

System-on-chip testability using LSSD scan structures

A technology-independent test synthesis tool extends the basic level-sensitive scan design (LSSD) boundary scan methodology. It reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay.

Automatic insertion of scan structure to enhance testability of embedded memories, cores and chips

This paper describes a technology independent test synthesis framework to enhance the testability of embedded memories, cores and chips using extended LSSD boundary scan methodology. Extended LSSD boundary scan reuses functional storage elements and therefore introduces minimal test logic overhead and delay. Automatic insertion of this DFT methodology is particularly challenging since it involves identification and reconfiguration of the functional latches and logic transformations of I/O cells. Experimental results demonstrate the productivity gained using the proposed test synthesis framework as well as the overlead induced by the proposed DFT method.

Defect analysis and a new fault model for multi-port SRAMs

Semiconductor memory failures depend on the behavior of its components. This paper deals with testing of defects occurring in the memory cells of a multi-port memory. We also consider the resistive shorts between word/bit lines of same and different ports of the memory. The memory is modeled at the transistor level and analyzed for electrical defects by applying a set of patterns. Not only have existing models been taken into account in our simulation but also a new fault model for the multi-port memory is introduced. The boundaries of failure for the proposed defects are identified.

Automatic generation and compaction of March tests for memory arrays

Given a set of memory array faults, the problem of computing a compact March test that detects all specified memory array faults is addressed. In this paper, we propose a novel approach in which every memory array fault is modeled by a set of primitive memory faults. A primitive March test is defined for each primitive memory fault. We show that March tests that detect the specified memory array faults are composed of primitive March tests. A method to compact the March tests for the specified memory array faults is described. A set of examples to illustrate the approach is presented. Experimental results demonstrate the productivity gained using the proposed framework.