Scott Koziol

A Floating-Gate-Based Field-Programmable Analog Array

A field-programmable analog array (FPAA) with 32 computational analog blocks (CABs) and occupying 3 × 3 mm2 in 0.35-μm CMOS is presented. Each CAB has a wide variety of subcircuits ranging in granularity from multipliers and programmable offset wide-linear-range Gm blocks to nMOS and pMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating-gate (FG) transistors, the total number of which exceeds fifty thousand. Using FG devices eliminates the need for SRAM to store configuration bits since the switch stores its own configuration. This system exhibits significant performance enhancements over its predecessor in terms of achievable dynamic range (> 9 b of FG voltage) and speed (≈ 20 gates/s) of accurate FG current programming and isolation between ON and OFF switches. An improved routing fabric has been designed that includes nearest neighbor connections to minimize the penalty on bandwidth due to routing parasitic. A maximum bandwidth of 57 MHz through the switch matrix and around 5 MHz for a first-order low-pass filter is achievable on this chip, the limitation being a “program” mode switch that will be rectified in the next chip. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Measured results of the individual subcircuits and two system examples including an AM receiver and a speech processor are presented.

Neural Dynamics in Reconfigurable Silicon

A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm2.

Hardware and software infrastructure for a family of floating-gate based FPAAs

Analog circuits and systems research and education can benefit from the flexibility provided by large-scale Field Programmable Analog Arrays (FPAAs). This paper presents the hardware and software infrastructure supporting the use of a family of floating-gate based FPAAs being developed at Georgia Tech. This infrastructure is compact and portable and provides the user with a comprehensive set of tools for custom analog circuit design and implementation. The infrastructure includes the FPAA IC, discrete ADC, DAC and amplifier ICs, a 32-Bit ARM based microcontroller for interfacing the FPAA with the users computer, and Matlab and targeting software. The FPAA hardware communicates with Matlab over a USB connection. The USB connection also provides the hardwares power. The software tools include three major systems: a Matlab Simulink FPAA program, a SPICE to FPAA compiler called GRASPER, and a visualization tool called RAT. The hardware consists of two custom PCB designs which include a main board used to program and control an FPAA IC and an FPAA IC adaptor board used to interface a QFP packaged FPAA IC with the 100 pin ZIF socket on the main programming and control board.

RASP 2.8: A new generation of floating-gate based field programmable analog array

The RASP 2.8 is a very powerful reconfigurable analog computing platform with thirty-two computational analog blocks (CABs). Each CAB has a wide variety of sub-circuits ranging in granularity from multipliers and programmable offset wide linear range Gm blocks to NMOS and PMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating gate transistors. This system exhibits significant performance enhancements over its predecessor in terms of achievable signal bandwidth (> 50 MHz), accuracy (> 9 bits), dynamic range (> 7 decades of current), speed of floating-gate programming (> 200 gates/sec) and isolation between ON and OFF switches. The improved bandwidth is primarily due to an improved routing fabric that includes nearest neighbor connections. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Several complex system examples are presented.

Modeling and Implementation of Voltage-Mode CMOS Dendrites on a Reconfigurable Analog Platform

Many decades ago, Wilfrid Rall and others laid the foundations for mathematical modeling of dendrites using cable theory. With reconfigurable analog architectures, we are now able to accurately program different circuit architectures to emulate dendrites. Our work has shown that these circuits accurately reproduce results predicted from cable theory when inputs to the system are small. For large inputs, interesting nonlinear effects begin to take hold.

A Neuromorphic Approach to Path Planning Using a Reconfigurable Neuron Array IC

This paper presents hardware results for a neuromorphic approach to path planning using a neuron array integrated circuit. The algorithm is explained and experimental results are presented showing 100% correct and optimal performance for a large number of randomized maze environment scenarios. Based on neuron signal propagation speed, neuron integrated circuit (IC) path planning may offer a computational advantage over state-of-the-art wavefront planners implemented on field-programmable gate arrays (FPGAs). Analytical time and space complexity metrics are developed in this paper for a neuron ICs planner, and these are verified against experimental data. Optimality and completeness are also addressed. The neuron structure allows one to develop sophisticated graphs with varied edge weights between nodes of the grid. Two interesting cases are presented. First, asymmetric edge costs are assigned to describe cases, which have a certain cost to travel a path in one direction, but a different cost to travel the same path but in the opposite direction. The application of this feature can translate to real world problems involving hills, traffic patterns, and so forth. Second, cases are presented where the nodes near an obstacle are given higher costs to visit these nodes. This is in an effort to keep the autonomous agent at a safe distance from obstacles. This grid weighting can also be used to differentiate among terrains such as sand, ice, gravel, or smooth pavement. Experimental results are presented for both cases.

Robot path planning using Field Programmable Analog Arrays

We present the successful application of reconfigurable Analog-Very-Large-Scale-Integrated (AVLSI) circuits to motion planning for the AmigoBot robot. Previous research has shown that custom application-specific-integrated-circuits (ASICs) can be used for robot path planning. However, ASICs are typically fixed circuit designs that require long fabrication times on the order of months. In contrast, our reconfigurable analog circuits called Field Programmable Analog Arrays (FPAAs) implement a variety of AVLSI circuits in minutes. We present experimental results of online robot path planning using FPAA circuitry, validating our assertion that FPAA-based AVLSI design is a feasible approach to computing complete motion plans using analog floating-gate resistive grids. We demonstrate the integration of FPAA hardware and software with a real robot platform and hardware in the loop simulations, present the trajectories developed by our planner and provide analysis of the time and space complexity of our proposed approach. The paper concludes by formulating metrics that identify domains where analog solutions to planning may be faster and more efficient than traditional, digital robot planning techniques.

Reconfigurable Analog VLSI circuits for robot path planning

This paper presents robot path planning using reconfigurable Analog-Very-Large-Scale-Integrated (AVLSI) circuits. Existing research has shown that custom AVLSI circuits known as application-specific-integrated-circuits (ASICs) can theoretically be used for robot path planning. There are two main drawbacks to using custom ASICs: 1) circuit designs are fixed to some extent (not changeable) and 2) long design cycle/fabrication time (order of months). Reconfigurable analog circuits called Field Programmable Analog Arrays (FPAAs) have been used to implement a variety of AVLSI circuits in a short time (order of minutes). This paper presents initial hardware results using reconfigurable AVLSI circuits developed at Georgia Tech to implement a robot path planning algorithm. A simple toy problem is presented as a proof of concept.

FPAA chips and tools as the center of an design-based analog systems education

The ever expanding research and commercialization activity around Large-Scale Field Programmable Analog Arrays (FPAA) asks the question whether we can broadly use these technologies in an educational environment. In fact, the research advances have been developed side by side with educational development, similar to what we saw for the early stages of digital VLSI design [1]. Previously, we demonstrated that FPAA could be used in a classical classroom laboratory setting where students could perform lab experiments given to them, and not just a topic for the academic research laboratory [2]. Over the next four years, we have made progress in using these devices, which has enabled wider use of these devices as well as enabling teaching system / signal-processing level projects to be attempted. These improvements include revamping one graduate course, focused on analog VLSI / system design, as a design based analog systems course where the students can experimentally measure the results of their design.

Transforming mixed-signal circuits class through SoC FPAA IC, PCB, and toolset

We present a SoC large-scale Field Programmable Analog Array (FPAA) test system, enabled by configurable analog-digital ICs to create a simple interface for a wide range of experiments in classroom environments. This configurable system appears as a simple digital peripheral using a standard USB interface for communication and power. Combined with a high-level tool flow for on-chip application design, this FPAA device demonstrates a number of mixed-signal computations, classification, and signal processing and its impact on hands-on circuit instruction.