Stephen Nease

A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena

We present a single-chip array of 100 biologically-based electronic neuron models interconnected to each other and the outside environment through 30,000 synapses. The chip was fabricated in a standard 350 nm CMOS IC process. Our approach used dense circuit models of synaptic behavior, including biological computation and learning, as well as transistor channel models. We use Address-Event Representation (AER) spike communication for inputs and outputs to this IC. We present the IC architecture and infrastructure, including IC chip, configuration tools, and testing platform. We present measurement of small network of neurons, measurement of STDP neuron dynamics, and measurement from a compiled spiking neuron WTA topology, all compiled into this IC.

A Programmable and Configurable Mixed-Mode FPAA SoC

This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and configurable blocks with a 16-bit open-source MSP430 microprocessor (μP) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits compiled into this architecture, and system measurements. A compiled analog acoustic command-word classifier on the FPAA SoC requires 23 μW to experimentally recognize the word dark in a TIMIT database phrase. This paper jointly optimizes high parameter density (number of programmable elements/area/process normalized), as well as high accessibility of the computations due to its data flow handling; the SoC FPAA is 600 000 × higher density than other non-FG approaches.

A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing

We present a field-programmable analog array designed for accurate low-power mixed-signal computation. This 25-mm2 350 nm-CMOS reconfigurable analog IC incorporates digital enhancements to increase compatibility in embedded mixed-signal systems. The chip contains 78 computational analog blocks (CABs) which house a variety of processing elements. There are 36 general CABs with hundreds of common analog primitives for computation, 18 digital-to-analog converter (DAC) CABs, each with 8-b compilable DAC capabilities, and 24 vector-matrix multiplier CABs, for low-power parallel processing. A floating-gate routing matrix connects these analog elements to one another, both within individual CABs and between CABs. To facilitate digital interfacing and dynamic reconfigurability, we included a novel network of volatile switches based on digital shift and select registers that control analog switches. These dynamically controlled switches span all of the rows and columns of the internal routing, allowing for run-time system modification and scanning I/O. The digital registers can also double as on-chip memory. We introduce a new hybrid floating-gate switch matrix, which includes switches that eliminate previously observed mismatch issues to provide highly precise computation. To highlight the potential of this digitally enhanced analog processor, we demonstrate a dynamically reconfigurable image transformer, an arbitrary waveform generator, and a mixed-signal FIR filter.

Modeling and Implementation of Voltage-Mode CMOS Dendrites on a Reconfigurable Analog Platform

Many decades ago, Wilfrid Rall and others laid the foundations for mathematical modeling of dendrites using cable theory. With reconfigurable analog architectures, we are now able to accurately program different circuit architectures to emulate dendrites. Our work has shown that these circuits accurately reproduce results predicted from cable theory when inputs to the system are small. For large inputs, interesting nonlinear effects begin to take hold.

2013 Special Issue: Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit

Results are presented from several spiking network experiments performed on a novel neuromorphic integrated circuit. The networks are discussed in terms of their computational significance, which includes applications such as arbitrary spatiotemporal pattern generation and recognition, winner-take-all competition, stable generation of rhythmic outputs, and volatile memory. Analogies to the behavior of real biological neural systems are also noted. The alternatives for implementing the same computations are discussed and compared from a computational efficiency standpoint, with the conclusion that implementing neural networks on neuromorphic hardware is significantly more power efficient than numerical integration of model equations on traditional digital hardware.

Transforming mixed-signal circuits class through SoC FPAA IC, PCB, and toolset

We present a SoC large-scale Field Programmable Analog Array (FPAA) test system, enabled by configurable analog-digital ICs to create a simple interface for a wide range of experiments in classroom environments. This configurable system appears as a simple digital peripheral using a standard USB interface for communication and power. Combined with a high-level tool flow for on-chip application design, this FPAA device demonstrates a number of mixed-signal computations, classification, and signal processing and its impact on hands-on circuit instruction.

STDP-enabled learning on a reconfigurable neuromorphic platform

Spike-Timing Dependent Plasticity (STDP) is a well-known mechanism that implements learning in biological neural networks. We have developed a neuromorphic integrated circuit which contains 100 neurons and 30,000 synapses, 20,000 of which can follow an STDP learning rule. This work presents the initial results for circuits utilizing STDP on this chip.

A mixed-mode FPAA SoC for analog-enhanced signal processing

We present the RASP 2.9v, an FPAA for mixed-signal computation with an emphasis on enhanced digital support. This 25mm2, 350nm CMOS chip includes on-chip compilable DACs, dynamic reconfigurability and digital storage, and 76,000 programmable elements. We demonstrate an analog image-transform processor, an arbitrary waveform generator, and a mixed-mode FIR filter.

SoC FPAA IC, PCB, and tool demonstration

This demonstration presents live hands-on experience of the System on Chip (SoC) large-scale Field Programmable Analog Array (FPAA) IC [1] through a complete PC Board and high-level tool interface [2]. Figure 1a shows the demonstration requires only basic power connection to the laptop The hardware includes an FPAA demonstration board and a Digilent USB device to enable a scope / function generator functionality.