Jennifer Hasler

Finding a roadmap to achieve large neuromorphic hardware systems

Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moores law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

A Programmable and Configurable Mixed-Mode FPAA SoC

This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and configurable blocks with a 16-bit open-source MSP430 microprocessor (μP) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits compiled into this architecture, and system measurements. A compiled analog acoustic command-word classifier on the FPAA SoC requires 23 μW to experimentally recognize the word dark in a TIMIT database phrase. This paper jointly optimizes high parameter density (number of programmable elements/area/process normalized), as well as high accessibility of the computations due to its data flow handling; the SoC FPAA is 600 000 × higher density than other non-FG approaches.

Vector-Matrix Multiply and Winner-Take-All as an Analog Classifier

The vector-matrix multiply and winner-take-all structure is presented as a general-purpose, low-power, compact, programmable classifier architecture that is capable of greater computation than a one-layer neural network, and equivalent to a two-layer perceptron. The classifier generates event outputs and is suitable for integration with event-driven systems. The main sources of mismatch, temperature dependence, and methods for compensation are discussed. We present measured data from simple linear and nonlinear classifier structures on a 0.35-μm chip and analyze the power and computing efficiency for scaled structures.

Integrated Floating-Gate Programming Environment for System-Level ICs

We present the first integrated system to handle heterogeneously used and programmed floating-gate (FG) elements in a single modular approach. We focus on IC design, integration, characterization, and algorithmic development of an integrated FG programming system for a large-scale field-programmable analog array. We work through tunneling approaches to initialize the FG devices for precision programming, as well as hot-electron injection approaches for precise device programming.

High-Level Modeling of Analog Computational Elements for Signal Processing Applications

Large-scale field-programmable analog array ICs have made analog and analog-digital signal processing techniques accessible to a much wider community. Given this opportunity, we present a framework for considering analog signal processing (ASP) techniques for low-power systems. The core of this paper is the definition of an analog abstraction methodology and the creation of a library of high-level analog computation blocks. By abstracting the analog design, we ensure that users have a similar experience to what they would expect with digital design, thus empowering system-level engineers to take advantage of ASP concepts. The result of this paper is to pull analog computation toward system-level development, comparable with the trend in digital system design over the last 30 years.

FPAA/Memristor Hybrid Computing Infrastructure

This paper presents a circuit in which tungsten oxide -based analog memristors are post-processed on a CMOS-based Field-Programmable Analog Array Integrated Circuit (FPAA-IC). FPAAs are powerful tools for rapid analog experimentation, prototyping and power-efficient computing, and they allow custom analog circuits to be built and reconfigured. The primary motivation for this work is to introduce and demonstrate the operation of the FPAA/memristor hybrid circuit and the board-level infrastructure, and to form a basis for subsequent empirical work on analog memristive computing. The experiments shown in this paper demonstrate a successful fabrication of memristors on the FPAA substrate, and the usefulness of the hybrid computing infrastructure in terms of experimentation with memristors. The experiments suggest that a single state variable cannot capture the adaptation of a memristor. To this end, a SPICE compatible memristor model with two state variables is presented. Furthermore, a memristor-based adaptive coincidence detector is demonstrated on the FPAA/Memristor computing infrastructure.

Adaptive Floating-Gate Circuit Enabled Large-Scale FPAA

We present a large-scale field programmable analog array that enables floating-gate (FG) adaptive circuits using FG-based switch technology. We present a novel architecture technology that enables switch routing with FG elements for signals resulting from high voltage adapting FG elements. We present careful analysis and characterization of the FG structure, including programming ranges, electron tunneling paths, to show the indirect programming structure involving an nFET device can handle the signals. We present the experimental data (350-nm commercial CMOS process) for a single-transistor adaptive structure, for a compiled autozeroing amplifier, and for multiple adaptive FG circuits.

A Neuromorphic Approach to Path Planning Using a Reconfigurable Neuron Array IC

This paper presents hardware results for a neuromorphic approach to path planning using a neuron array integrated circuit. The algorithm is explained and experimental results are presented showing 100% correct and optimal performance for a large number of randomized maze environment scenarios. Based on neuron signal propagation speed, neuron integrated circuit (IC) path planning may offer a computational advantage over state-of-the-art wavefront planners implemented on field-programmable gate arrays (FPGAs). Analytical time and space complexity metrics are developed in this paper for a neuron ICs planner, and these are verified against experimental data. Optimality and completeness are also addressed. The neuron structure allows one to develop sophisticated graphs with varied edge weights between nodes of the grid. Two interesting cases are presented. First, asymmetric edge costs are assigned to describe cases, which have a certain cost to travel a path in one direction, but a different cost to travel the same path but in the opposite direction. The application of this feature can translate to real world problems involving hills, traffic patterns, and so forth. Second, cases are presented where the nodes near an obstacle are given higher costs to visit these nodes. This is in an effort to keep the autonomous agent at a safe distance from obstacles. This grid weighting can also be used to differentiate among terrains such as sand, ice, gravel, or smooth pavement. Experimental results are presented for both cases.

Speech Processing on a Reconfigurable Analog Platform

Real-time implementation of audio processing algorithms involving discrete-time signals tend to be power-intensive. We present an alternate analog system implementation of a noise-suppression algorithm on our reconfigurable chip, which also enables future implementations of other applications such as voice-activity detection, hearing compensation, and classifier front-ends.