Scott Monaghan

A systematic study of (NH4)2S passivation (22%, 10%, 5%, or 1%) on the interface properties of the Al2O3/In0.53Ga0.47As/InP system for n-type and p-type In0.53Ga0.47As epitaxial layers

In this work, we present the results of an investigation into the effectiveness of varying ammonium sulphide (NH4)2S concentrations in the passivation of n-type and p-type In0.53Ga0.47As. Samples were degreased and immersed in aqueous (NH4)2S solutions of concentrations 22%, 10%, 5%, or 1% for 20 min at 295 K, immediately prior to atomic layer deposition of Al2O3. Multi-frequency capacitance-voltage (C-V) results on capacitor structures indicate that the lowest frequency dispersion over the bias range examined occurs for n-type and p-type devices treated with the 10%(NH4)2S solution. The deleterious effect on device behavior of increased ambient exposure time after removal from 10%(NH4)2S solution is also presented. Estimations of the interface state defect density (Dit) for the optimum 10%(NH4)2S passivated In0.53Ga0.47As devices extracted using an approximation to the conductance method, and also extracted using the temperature-modified high-low frequency C-V method, indicate that the same defect is pre...

Temperature and frequency dependent electrical characterization of HfO2/InxGa1−xAs interfaces using capacitance-voltage and conductance methods

Electrical properties of metal-oxide-semiconductor capacitors using atomic layer deposited HfO2 on n-type GaAs or InxGa1−xAs (x=0.53, 0.30, 0.15) epitaxial layers were investigated. Capacitance-voltage (CV) measurements indicated large temperature and frequency dispersion at positive gate bias in devices using n-type GaAs and low In content (x=0.30, 0.15) InxGa1−xAs layers, which is significantly reduced for devices using In0.53Ga0.47As. For In0.53Ga0.47As devices, the CV response at negative gate bias is most likely characteristic of an interface state response and may not be indicative of true inversion. The conductance technique on Pd/HfO2/In0.53Ga0.47As/InP shows reductions in interface state densities by In0.53Ga0.47As surface passivation and forming gas annealing (325 °C).

Impact of Forming Gas Annealing on the Performance of Surface-Channel

We investigated the effect of forming gas (5% H₂/95% N₂) annealing on surface-channel In_0.53 Ga_0.47As MOSFETs with atomic-layer-deposited Al₂O₃ as the gate dielectric. We found that a forming gas anneal (FGA) at 300°C for 30 min was efficient at removing or passivating positive fixed charges in Al₂O₃ , resulting in a shift of the threshold voltage from -0.63 to 0.43 V and in an increase in the <i>I</i>_on/<i>I</i>_off ratio of three orders of magnitude. Following FGA, the MOSFETs exhibited a subthreshold swing of 150 mV/dec, and the peak transconductance, drive current, and peak effective mobility increased by 29%, 25%, and 15%, respectively. FGA significantly improved the source- or drain-to-substrate junction isolation, with a reduction of two orders of magnitude in the reverse bias leakage exhibited by the Si-implanted In_0.53Ga_0.47As n⁺/p junctions, which is consistent with passivation of midgap defects in In_0.53Ga_0.47As by the FGA process.

\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}

High dielectric constant hafnium oxide films were formed by electron beam (e-beam) evaporation on HF last terminated silicon (100) wafers. We report on the influence of low energy argon plasma ( ∼ 70 eV) and oxygen flow rate on the electrical, chemical, and structural properties of metal-insulator-silicon structures incorporating these e-beam deposited HfO2 films. The use of the film-densifying low energy argon plasma during the deposition results in an increase in the equivalent oxide thickness (EOT) values. We employ high resolution transmission electron microscopy (HRTEM), x-ray photoelectron spectroscopy (XPS), and medium energy ion scattering experiments to investigate and understand the mechanisms leading to the EOT increase. We demonstrate very good agreement between the interfacial silicon oxide thicknesses derived independently from XPS and HRTEM measurements. We find that the e-beam evaporation technique enabled us to control the SiOx interfacial layer thickness down to ∼ 6 A. Very low leakage current density (<10−4 A/cm2) is measured at flatband voltage +1 V into accumulation for an estimated EOT of 10.9±0.1 A. Based on a combined HRTEM and capacitance-voltage (CV) analysis, employing a quantum-mechanical CV fitting procedure, we determine the dielectric constant (k) of HfO2 films, and associated interfacial SiOx layers, formed under various processing conditions. The k values are found to be 21.2 for HfO2 and 6.3 for the thinnest ( ∼ 6 A) SiOx interfacial layer. The cross-wafer variations in the physical and electrical properties of the HfO2 films are presented.

MOSFETs With an ALD

In this work, we present the results of an investigation into charge trapping in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOS capacitors), which is analysed using the hysteresis exhibited in the capacitance-voltage (C-V) response. The availability of both n and p doped In0.53Ga0.47As epitaxial layers allows the investigation of both hole and electron trapping in the bulk of HfO2 and Al2O3 films formed using atomic layer deposition (ALD). The HfO2/In0.53Ga0.47As and Al2O3/In0.53Ga0.47As MOS capacitors exhibit an almost reversible trapping behaviour, where the density of trapped charge is of a similar level to high-k/In0.53Ga0.47As interface state density, for both electrons and holes in the HfO2 and Al2O3 films. The experimental results demonstrate that the magnitude of the C-V hysteresis increases significantly for samples which have a native oxide layer present between the In0.53Ga0.47As surface and the high-k oxide, suggesting that the charge trapping responsible for the C-V hys...

\hbox{Al}_{2}\hbox{O}_{3}

The electrical properties of metal-oxide-semiconductor capacitors incorporating atomic layer deposited Al2O3 on n-type and p-type In0.53Ga0.47As were investigated. A clear minority carrier response was observed for both n-type and p-type Au/Ni/Al2O3/In0.53Ga0.47As devices following an optimized ammonium sulfide (NH4)2S treatment. Capacitance-voltage and conductance-voltage measurements performed at varying temperatures allowed an Arrhenius extraction of activation energies for the minority carrier response, indicating a transition from a generation-recombination regime to a diffusion controlled response.

Gate Dielectric

High mobility III-V substrates with high-k oxides are required for device scaling without loss of channel mobility. Interest has focused on the self-cleaning effect on selected III-V substrates during atomic layer deposition of Al2O3. A thin (∼1 nm) Al2O3 interface control layer is deposited on In0.53Ga0.47As prior to HfO2 growth, providing the benefit of self-cleaning and improving the interface quality by reducing interface state defect densities by ∼50% while maintaining scaling trends. Significant reductions in leakage current density and increased breakdown voltage are found, indicative of a band structure improvement due to the reduction/removal of the In0.53Ga0.47As native oxides.

Electrical, structural, and chemical properties of HfO2 films formed by electron beam evaporation

This work focuses on the separation and quantification of fixed bulk oxide charge, fixed charge at the dielectric-semiconductor interface and interface state charge components in the Pt/Al 2 O 3 /In 0.53 Ga 0.47 As metal-oxide-semiconductor (MOS) system. The availability of atomic layer deposited Al 2 O 3 dielectrics over n- and p-type In 0.53 Ga 0.47 As with a range of well-controlled thickness values opens up an experimental route for the determination of the interface state density (D it ) independently of the total fixed oxide charge using capacitance-voltage measurements taken at 1 MHz and -50°C. Low temperature forming gas annealing (350°C) significantly reduces the amount of fixed charge. The interface fixed charge is reduced from ~ -8.5 x 10 12 cm -2 preanneal to ~-7.4 × 10 11 cm -2 postanneal and the bulk oxide charge is reduced from ~1.4 x 10 19 cm -3 preanneal to ~5 x 10 1 cm -3 postanneal. The forming gas anneal also has a significant effect on the interface state charge, reducing its density from 1.3 x 10 13 cm -2 preanneal to 4 x 10 12 cm -2 postanneal.

An investigation of capacitance-voltage hysteresis in metal/high-k/In0.53Ga0.47As metal-oxide-semiconductor capacitors

In this paper, we present a review of experimental results examining charged defect components in the Al₂O₃/In_0.53Ga_0.47As metal-oxide-semiconductor (MOS) system. For the analysis of fixed oxide charge and interface state density, an approach is described where the flatband voltage for n- and p-type Al₂O₃/In_0.53Ga_0.47As MOS structures is used to separate and quantify the contributions of fixed oxide charge and interface state density. Based on an Al₂O₃ thickness series (10-20 nm) for the n- and p-type In_0.53Ga_0.47As layers, the analysis reveals a positive fixed charge density ( ~ 9 ×10¹⁸ cm^-3) distributed throughout the Al₂O₃ and a negative sheet charge density (- 8 × 10¹² cm^-2) located near the Al₂O₃/In_0.53Ga_0.47As interface. The interface state density integrated across the energy gap is ~1 ×10¹³ cm^-2 and is a donor-type (+/0) defect. The density of the fixed oxide charge components is significantly reduced by forming gas (5 % H₂/ 95% N₂ ambient at 350 °C for 30 minutes) annealing. The interface state distribution obtained from multi-frequency capacitance-voltage and conductance-voltage measurements on either MOS structures or MOSFETs indicates a peak density located around the In_0.53Ga_0.47As midgap energy, with a sharp increase in the interface state density toward the valance band and evidence of interface states aligned with the In_0.53Ga_0.47As conduction band. The integrated interface state density obtained from multi-frequency capacitance-voltage and conductance-voltage analysis is in good agreement with the approach of comparing the flatband voltages in n- and p -type Al₂O₃/In_0.53Ga_0.47As MOS structures. Finally, this paper reviews recent work based on an optimization of the In_0.53Ga_0.47As surface preparation using (NH₄)₂S, combined with minimizing the transfer time to the atomic layer deposition reactor for Al₂O₃, which indicates interface state reduction and genuine surface inversion for both n- and p -type Al₂O₃/In_0.53Ga_0.47As MOS structures.

Analysis of the minority carrier response of n-type and p-type Au/Ni/Al2O3/In0.53Ga0.47As/InP capacitors following an optimized (NH4)2S treatment

The atomic layer deposition of high dielectric constant oxides like HfO2 on III-V substrates such as In0.53Ga0.47As leads to a poor interface, with the growth of In0.53Ga0.47As native oxides regardless of the surface pretreatment and passivation method. The presence of the native oxides leads to poor gate leakage current characteristics due to the low band gap of the native oxides and the presence of potential wells at the interface. In addition, the poor quality of this interface leads to very large interface state defect densities, which are detrimental to metal-oxide-semiconductor-based device performance. A wide band gap interlayer replacing the native oxide layer would remove the potential wells and provide a larger barrier to conduction. It may also assist in the improvement of the interface quality, but the problem remains as to how this native oxide interlayer cannot only be removed but prevented from regrowing. In this regard, the authors present electrical results showing that the atomic layer d...