Sebastià A. Bota

Impact of Thermal Gradients on Clock Skew and Testing

In this article, we analyze the impact of within-die thermal gradients on clock skew, considering temperatures effect on active devices and the interconnect system. This effect, along with the fact that the test-induced thermal map can differ from the normal-mode thermal map, motivates the need for a careful consideration of the impact of temperature gradients on delay during test. After our analysis, we propose a dual-VDD clocking strategy that reduces temperature-related clock skew effects during test. Clock network design is a critical task in developing high-performance circuits because circuit performance and functionality depend directly on this subsystems performance. When distributing the clock signal over the chip, clock edges might reach various circuit registers at different times. The difference in clock arrival time between the first and last registers receiving the signal is called clock skew. With tens of millions of transistors integrated on the chip, distributing the clock signal with near-zero skew introduces important constraints in the clock distribution networks physical implementation and affects overall circuit power and area

An Experimental Approach to Accurate Alpha-SER Modeling and Optimization Through Design Parameters in 6T SRAM Cells for Deep-Nanometer CMOS

We report a detailed analysis about the memory soft error rate (SER) dependence with transistor design parameters for six-transistor (6T) SRAM cells fabricated on a 65-nm CMOS commercial technology. SER data are obtained from accelerated test with an Am-241 alpha source. Five 6T cells with different nMOS and pMOS transistors size combinations were fabricated and characterized. After verifying that transistor width increase always provides higher critical charge values, SER data show that this value is improved only when increasing the pMOS transistors width. Memory cells containing non-minimum-width nMOS transistors always exhibit worse SER values than cells with minimum-size ones. In addition, one cell with a higher Qcrit than another can show a worse SER depending on the transistor type whose size is being enlarged. Accordingly to this, we have found that SER may be increased by 76% without modifying cell structure nor impacting cell area. This behavior is qualitatively and quantitatively explained through an analytical model that relates SER to Qcrit and the transistor design parameters.

Alternate characterization technique for static random-access memory static noise margin determination

The cell static noise margin (SNM) is widely used as a stability criterion for static random-access memory cells design. This parameter is typically determined through electrical simulations since direct experimental characterization of SNM is not achievable. In this work, we present a methodology that provides an indirect measurement of the SNM on a per-cell basis for six-transistor SRAMs. It is based on combining an Adaptive Neuro-Fuzzy Inference System (ANFIS) with circuit-level cell experimentally measurable parameters as input variables to the tool. We show that it is possible to obtain the SNM for individual memory cells using the same experimental setup and data than that required for shmoo plot measurements. Results confirm that the SNM can be experimentally estimated with a relative error compared with electrical simulations that is below 0.5%. Copyright

Analysis of radiation-hardening techniques for 6T SRAMs with structured layouts

We analyze two complementary radiation-hardening techniques for 6T SRAM memories compatible with structured layouts. One approach relies on the individual selection of the threshold voltage of each of the four transistors forming the cross-coupled inverters of the SRAM cell. The other one is based on the modification of the widths of all pmos or all nmos transistors of the cell. The first technique does not affect the cell layout. The second one increases the minimum width of all pmos by a factor cp and the minimum width of all nmos by a factor cn. This prevents the formation of diffusion bends, allowing structured layouts. Both techniques provide an improvement in SEU robustness.

FinFET SRAM hardening through design and technology parameters considering process variations

Radiation-induced soft errors have become one of the most important reliability concerns in the nanometer regime. In this paper, we analyze two alternatives to improve FinFET-based SRAM cell hardening. One is related to increasing the number of fins of the transistors composing the cross-coupled inverters. This option provides a significant increase of the cell critical charge (Qcrit), but with a cost in area. The other alternative increases the transistors fin height. Results show that a similar Qcrit gain is achieved by increasing the fin height instead of the number of fins without area overhead. The impact of process variations has been considered. Qcrit distribution has been modeled through an statistical approach based on Design of Experiments. Results are presented for a 10nm-SOI Trigate FinFET technology.

Pass-transistors pMOS based 8T SRAM cell for layout compaction

We present a new 8-transistor (8T) SRAM cell design that uses pMOS devices as cell pass transistors controlled by the write word-line signal. The main advantage of this schema is the composition of a balanced 8T SRAM cell having four nMOS and four pMOS transistor that enables a more compact layout and area reduction. An exhaustive analysis about the impact on key parameters such as leakage consumption, write and read stability margins, read delay time and single event upsets for the new cell is reported. A trade-off between cell area reduction and write noise margin improvement is observed, while the remaining parameters are not impacted.

SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results

Experimental results from a 65 nm CMOS commercial technology SRAM test chip reveal a linear correlation between a new electrical parameter -the word-line voltage margin (VWLVM)- and the measured circuit alpha-SER. Additional experiments show that no other memory cell electrical robustness-related parameters exhibit such correlation. The technique proposed is based on correlating the VWLVM to the SER measured on a small number of circuit samples to determine the correlation parameters. Then, the remaining non-irradiated circuits SER is determined from electrical measurements (VWLVM) without the need of additional radiation experiments. This method represents a significant improvement in time and cost, while simplifying the SER-determination methods since most of the circuits do not require irradiation. The technique involves a minor memory design modification that does not degrade circuit performance, while circuit area increase is negligible.

Analysis of fin height on FinFET SRAM cell hardening

Radiation soft reliability is showing a declining with technology scaling. Because of this new techniques are required to add resilience to the chips. In this work, we analyze the impact of channel width modulation of FinFET SRAM cell transistors by increasing the fin height of FinFET transistor on FinFET SRAM cell hardening. TCAD simulations of the memory cell are carried-out. Results are presented for a 10nm-SOI Tri-Gate FinFET technology. We show that increasing the fin height of FinFET SRAM cell transistors, may not be effective to improve SRAM cell hardening to heavy ions.

An SET propagation EDA tool based on analytical glitch propagation model

We present a complete EDA tool that quantifies the susceptibility of each node within a combinational circuit to SET propagation. The tool includes a fully analytical SET propagation model developed previously and considers both electrical and logic masking. After an initial path pruning phase based on logical analysis to determine true paths, the tool computes the minimum width and minimum height SET pulse propagating from each circuit node towards the circuit outputs. Internal nodes are ranked depending on its SET propagation susceptibility providing valuable information to the circuit designer about the weakest circuit nodes against ionizing radiation. Tool results are compared to exhaustive electrical-level simulations for a commercial 65nm CMOS technology and a 45nm open-cell technology showing excellent results.

Single event transients generation in silicon devices with pulsed laser

We perform a comparative study of the characteristics and capabilities of a pulsed laser system that emulates single event injection available at the UIB with respect to similar pulsed laser test facilities in Europe (EADS, IMS) and the United States (JPL, NRL). A series of experimental measurements were taken on a silicon photodiode (Centronic OSD15-5T) used in a previous comparative study conducted by the mentioned centers.