Jaume Verd

Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories

Error correction codes combined with built-in current sensors (BICS) have been proposed as an effective technique to detect and correct SEU errors in memories. As technology scales down, multiple bit upsets affecting the same word are becoming more common as cell density increases. In this work we propose a Cross-BICS monitoring architecture to enhance SEU detection and correction in SRAM memories. The proposed architecture uses two types of BICS: one monitors the same-row cells (through power lines), while the other monitors the same–column cells (through bit lines).

Memory State Transient Analysis (MSTA): A New Soft Error Rate Measurement Method for CMOS Memory Elements Based on Stochastic Analysis

We analyze the evolution of SRAM memory logic contents under irradiation by defining the memory state as the number of cells storing a given logic value (i.e. number of cells storing a logic-1). We find that the memory state evolution under irradiation follows an Ehrenfest urn model due to the constant effect of single event upsets, and that in large memories it can be associated to an Ornstein-Uhlenbeck process. Memory state transient analysis has been applied to determine the device Soft error rate for an SRAM fabricated in a 65 nm commercial CMOS process obtaining a very good correlation. Furthermore, our analysis shows that the technique is applicable to systems composed by various dissimilar memory components, providing-under certain circumstances-the specific Soft Error Rate of each component.

Top-side pulsed laser induced single event upsets in highly-scaled SRAM devices

A pulsed laser system has been used to induce single event upsets (SEU) in highly-scaled SRAM devices. The events are induced from the circuit topside in areas where the higher metal layers have been eliminated by design from the circuit layout. The presence of metal tracks for voltage biasing, bit-line and word-line routing, difficult carrying out measurements to obtain the minimum energy required to induce an SEU. Off-chip transient currents caused by laser pulses have been measured; data indicates that most of such current is due to photocurrents generated in the well-substrate diode.

Thermomechanical Noise Characterization in Fully Monolithic CMOS-MEMS Resonators

We analyzed experimentally the noise characteristics of fully integrated CMOS-MEMS resonators to determine the overall thermomechanical noise and its impact on the limit of detection at the system level. Measurements from four MEMS resonator geometries designed for ultrasensitive detection operating between 2-MHz and 8-MHz monolithically integrated with a low-noise CMOS capacitive readout circuit were analyzed and used to determine the resolution achieved in terms of displacement and capacitance variation. The CMOS-MEMS system provides unprecedented detection resolution of 11 yF·Hz−1/2 equivalent to a minimum detectable displacement (MDD) of 13 fm·Hz−1/2, enabling noise characterization that is experimentally demonstrated by thermomechanical noise detection and compared to theoretical model values.

A 0.35-μm CMOS-MEMS Oscillator for High-Resolution Distributed Mass Detection

This paper presents the design, fabrication, and electrical characterization of an electrostatically actuated and capacitive sensed 2-MHz plate resonator structure that exhibits a predicted mass sensitivity of ~250 pg·cm−2·Hz−1. The resonator is embedded in a fully on-chip Pierce oscillator scheme, thus obtaining a quasi-digital output sensor with a short-term frequency stability of 1.2 Hz (0.63 ppm) in air conditions, corresponding to an equivalent mass noise floor as low as 300 pg·cm−2. The monolithic CMOS-MEMS sensor device is fabricated using a commercial 0.35-μm 2-poly-4-metal complementary metal-oxide-semiconductor (CMOS) process, thus featuring low cost, batch production, fast turnaround time, and an easy platform for prototyping distributed mass sensors with unprecedented mass resolution for this kind of devices.

Cantilever NEMS relay-based SRAM devices for enhanced reliability

We analyze the benefits of replacing selected MOSFET transistors by nanoelectromechanical relays within conventional CMOS six transistor SRAM cells. Specifically, we evaluate a potential implementation that uses a cantilever designed with a 65 nm standard CMOS technology. The impact on various reliability metrics like static noise margin and write noise margin are evaluated from circuit simulations using a nanomechanical relay Verilog-A compact model. Comparisons are performed between a 65 nm CMOS 6T conventional SRAM cell and various hybrid memory cells constructed by replacing selected MOSFET transistors with cantilever relays. The impact on other important memory cell parameters such as area, timing performance and power consumption is also discussed.

Improvement of the chaotic response in MEMS with fuzzy control implemented by ANN

Even when the conditions to achieve robust chaotic response in nonlinear MEMS oscillators are verified, the attainment of the proper parameters for chaotic signal generation is not immediate. This paper presents for the first time a control method based on fuzzy logic and artificial neural networks to maximize the chaotic response, and tests its effectiveness through numerical simulations of a cc-beam MEMS resonator model designed in a commercial CMOS technology.

Multi-subject Project Based Learning initiative

This paper presents the initiative aimed to increase the number of collaborative activities and the motivation of students for engineer topics. The work centers the attention on the design and definition of a PjBL (Project Based Learning) initiative covering three different subjects. The main goal of this work is to develop social and collaborative skills not only between the partners of the same subject, but also between students from different generations and courses. The work proposes a multi-subject PBL (Problem Based Learning) activity where expert members from different subjects train to students groups. The initiative, which is carried out in the last courses of an undergraduate program, has been well received by students with having a direct impact on their motivation. In any case, but some aspects need to be planned with more deeply: coordination between students from different subjects and impact of the student groups that do not finish the activity.

A CMOS integrated system for SEE-induced transients acquisition

We present the design and operation of a monitor circuit that captures the effect of ionizing particles on sensitive CMOS IC internal nodes. The circuit implements a Single Event Effects (SEE) detector and a quick sampling block that captures the SEE induced waveform shape currents during a certain time window. These values can be read externally through a dedicated decoding circuitry. The circuit has been designed and fabricated on a 130nm technology. Preliminary experimental results and detailed simulations are provided to demonstrate the feasibility of the system implemented.