Seethambal S. Mani

Effect of W coating on microengine performance

Two major problems associated with Si-based MEMS (MicroElectroMechanical Systems) devices are stiction and wear. Surface modifications are needed to reduce both adhesion and friction in micromechanical structures to solve these problems. In this paper, we will present a CVD (Chemical Vapor Deposition) process that selectively coats MEMS devices with tungsten and significantly enhances device durability. Tungsten CVD is used in the integrated-circuit industry, which makes this approach manufacturable. This selective deposition process results in a very conformal coating and can potentially address both stiction and wear problems confronting MEMS processing. The selective deposition of tungsten is accomplished through the silicon reduction of WF/sub 6/. The self-limiting nature of the process ensures consistent process control. The tungsten is deposited after the removal of the sacrificial oxides to minimize stress and process integration problems. The tungsten coating adheres well and is hard and conducting, which enhances performance for numerous devices. Furthermore, since the deposited tungsten infiltrates under adhered silicon parts and the volume of W deposited is less than the amount of Si consumed, it appears to be possible to release adhered parts that are contacted over small areas such as dimples. The wear resistance of tungsten coated parts has been shown to be significantly improved by microengine test structures.

Monolithic surface micromachined fluidic devices for dielectrophoretic preconcentration and routing of particles

We describe a batch fabrication process for producing encapsulated monolithic microfluidic structures. The process relies on sacrificial layers of silicon oxide to produce surface micromachined fluid channels. Bulk micromachined interconnects provide an interface between the microchannels and meso-scale fluidics. The full integration of the fabrication processing significantly increases device reproducibility and reduces long-term costs. The design and fabrication of dielectrophoresis (DEP) gating structures configured in both batch-flow and continuous-flow modes are detailed. Highly efficient microparticle preconcentration (up to ~100× in 100 s) and valving (97% particle routing efficiency) are demonstrated using ac DEP and an accompanying phase separation. The low aspect-ratio fluid channels with integrated microelectrodes are well suited for µm and sub-µm particle manipulation with electric fields.

Failure analysis of tungsten-coated polysilicon micromachined microengines

Failure analysis (FA) tools have been applied to analyze tungsten coated polysilicon microengines. These devices were stressed under accelerated conditions at ambient temperatures and pressure. Preliminary results illustrating the failure modes of microengines operated under variable humidity and ultra-high drive frequency will also be shown. Analysis os tungsten coated microengines revealed the absence of wear debris in microengines operated under ambient conditions. Plan view imagine of these microengines using scanning electron microscopy (SEM) revealed no accumulation of wear debris on the surface of the gears or ground plane on microengines operated under standard laboratory conditions. Friction bearing surfaces were exposed and analyzed using the focused ion beam (FIB). These cross sections revealed no accumulation of debris along friction bear surfaces. By using transmission electro microscopy (TEM) in conjunction with electron energy loss spectroscopy (EELS), we were able to identify the thickness, elemental analysis, and crystallographic properties of tungsten coated MEMS devices. Atomic force microscopy was also utilized to analyze the surface roughness of friction bearing surfaces.

A novel method of fabricating integrated FETs for MEMS applications

This paper demonstrates a simple technique for building n-channel MOSFETs and complex micromechanical systems simultaneously instead of serially, allowing a more straightforward integration of complete systems. The fabrication sequence uses few additional process steps and only one additional masking layer compared to a MEMS-only technology. The process flow forms the MOSFET gate electrode using the first level of mechanical polycrystalline silicon, while the MOSFET source and drain regions are formed by dopant diffusions into the substrate from subsequent levels of heavily doped poly that is used for mechanical elements. The process yields devices with good, repeatable electrical characteristics suitable for a wide range of digital and analog applications.

Stress and curvature in MEMS mirrors

The goal of this study is to understand how to optimize the performance of micro-mirrors for a variety of optical microsystem applications. Our approach relies on a number of process variations and mirror designs to ultimately produce relatively large (500μm to mm-scale), smooth (for nm RMS), and flat mirrors (greater than 1m curvature). White-light interferometric measurements, and finite element models are discussed in support of these findings. Stress gradients and residual stresses have been measured for accurate modeling of micro-mirrors. Through this modeling study, we have identified relevant structural parameters that will optimize SUMMiT V MEMS mirrors for optical applications. Ways of mitigating surface topography, print-through effects, and RMS roughness are currently being investigated.

Pin-joint design effect on the reliability of a polysilicon microengine

Accelerated stress experiments were performed on a class of pin joints to determine reliability. We varied parameters that affected the area of the rubbing surfaces and the gap between those surfaces. Most of the pin joints failed due to seizure. We observed bimodal failure distributions where the lower distribution was associated with an adhesion event with no observable wear debris. The upper distribution of failures was associated with agglomerations of wear debris, which may have seized the pin joint. The effect of surface coatings was also studied. We found that for supercritical carbon dioxide (SCCO/sub 2/) dried microengines; the largest effect was due to gap spacing. For microengines with a self-assembled monolayer coating (SAMS), we observed minimal difference in the lifetimes of failed devices.

Chemical vapor deposition coating for micromachines

Two major problems associated with Si-based MEMS devices are stiction and wear. Surface modifications are needed to reduce both adhesion and friction in micromechanical structures to solve these problems. In this paper, the authors will present a process used to selectively coat MEMS devices with tungsten using a CVD (Chemical Vapor Deposition) process. The selective W deposition process results in a very conformal coating and can potentially solve both stiction and wear problems confronting MEMS processing. The selective deposition of tungsten is accomplished through silicon reduction of WF{sub 6}, which results in a self-limiting reaction. The selective deposition of W only on polysilicon surfaces prevents electrical shorts. Further, the self-limiting nature of this selective W deposition process ensures the consistency necessary for process control. Selective tungsten is deposited after the removal of the sacrificial oxides to minimize process integration problems. This tungsten coating adheres well and is hard and conducting, requirements for device performance. Furthermore, since the deposited tungsten infiltrates under adhered silicon parts and the volume of W deposited is less than the amount of Si consumed, it appears to be possible to release stuck parts that are contacted over small areas such as dimples. Results from tungsten deposition on MEMS structures with dimples will be presented. The effect of wet and vapor phase cleanings prior to the deposition will be discussed along with other process details. The W coating improved wear by orders of magnitude compared to uncoated parts. Tungsten CVD is used in the integrated-circuit industry, which makes this approach manufacturable.

Optimizing galvanic pulse plating parameters to improve indium bump to bump bonding

The plating characteristics of a commercially available indium plating solution are examined and optimized to help meet the increasing performance demands of integrated circuits requiring substantial numbers of electrical interconnections over large areas. Current fabrication techniques rely on evaporation of soft metals, such as indium, into lift-off resist profiles. This becomes increasingly difficult to accomplish as pitches decrease and aspect ratios increase. To minimize pixel dimensions and maximize the number of pixels per unit area, lithography and electrochemical deposition (ECD) of indium has been investigated. Pulse ECD offers the capability of improving large area uniformity ideal for large area device hybridization. Electrochemical experimentation into lithographically patterned molds allow for large areas of bumps to be fabricated for low temperature indium to indium bonds. The galvanic pulse profile, in conjunction with the bath configuration, determines the uniformity of the plated array. This pulse is manipulated to produce optimal properties for hybridizing arrays of aligned and bonded indium bumps. The physical properties of the indium bump arrays are examined using a white light interferometer, a SEM and tensile pull testing. This paper provides details from the electroplating processes as well as conclusions leading to optimized plating conditions.

Injection molded microfluidic devices for biological sample separation and detection

We are developing a variety of microsystems for the separation and detection of biological samples. At the heart of these systems, inexpensive polymer microfluidic chips carry out sample preparation and analysis. Fabrication of polymer microfluidic chips involves the creation of a master in etched silicon or glass; plating of the master to produce a nickel stamp; large lot chip replication by injection molding; precision chip sealing; and chemical modification of channel surfaces. Separation chips rely on insulator-based dielectrophoresis for the separation of biological particles. Detection chips carry out capillary electrophoresis to detect fluorescent tags that identify specific biological samples. Since the performance and reliability of these microfluidic chips are very sensitive to fluidic impedance, electromagnetic flux, and zeta potential, the microchannel dimensions, shape, and surface chemistry have to be tightly controlled during chip fabrication and use. This paper will present an overview of chip design, fabrication, and testing. Dimensional metrology data, surface chemistry characterization, and chip performance data will be discussed in detail.

Fabrication and characterization of polymer microfluidic devices for bio-agent detection

Sandia and Lawrence Livermore National Laboratories are developing a briefcase-sized, broad-spectrum bioagent detection system. This autonomous instrument, the BioBriefcase, will monitor the environment and warn against bacterium, virus, and toxin based biological attacks. At the heart of this device, inexpensive polymer microfluidic chips will carry out sample preparation and analysis. Fabrication of polymer microfluidic chips involves the creation of a master in etched glass; plating of the master to produce a nickel stamp; large lot chip replication by injection molding; and thermal chip sealing. Since the performance and reliability of microfluidic chips are very sensitive to fluidic impedance and to electromagnetic fluxes, the microchannel dimensions and shape have to be tightly controlled during chip fabrication. In this talk, we will present an overview of chip design and fabrication. Metrology data collected at different fabrication steps and the dimensional deviations of the polymer chip from the original design will be discussed.