Bruce L. Draper

SEU-sensitive volumes in bulk and SOI SRAMs from first-principles calculations and experiments

Large-scale three-dimensional (3D) device simulations, focused ion microscopy, and broadbeam heavy-ion experiments are used to determine and compare the SEU-sensitive volumes of bulk-Si and SOI CMOS SRAMs. Single-event upset maps and cross-section curves calculated directly from 3D simulations show excellent agreement with broadbeam cross section curves and microbeam, charge collection and upset images for 16 K bulk-Si SRAMs. Charge-collection and single-event upset (SEU) experiments on 64 K and 1 M SOI SRAMs indicate that drain strikes can cause single-event upsets in SOI ICs. 3D simulations do not predict this result, which appears to be due to anomalous charge collection from the substrate through the buried oxide. This substrate charge-collection mechanism can considerably increase the SEU-sensitive volume of SOI SRAMs, and must be included in single-event models if they are to provide accurate predictions of SOI device response in radiation environments.

Impact of technology trends on SEU in CMOS SRAMs

The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. We study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation, to the development of a 0.5-/spl mu/m radiation-hardened CMOS SRAM is presented.

Accounting for Dose-Enhancement Effects with CMOS Transistors

Dose-enhancement effects are monitored with standard CMOS transistors by measuring thresholdvoltage shifts due to oxide-trapped charge and interface states. These results, in conjunction with studies of the effects of trapped-hole annealing and electron-hole recombination, are used to correlate the responses of transistors irradiated with Co-60 gamma rays or 10 keV X rays.

Comparison of enhanced device response and predicted X-ray dose enhancement effects on MOS oxides

The response of MOS capacitors to low- and medium-energy X-ray irradiation is investigated as a function of gate material (TaSi or Al), oxide thickness, and electric field. The measured device response is compared to the predicted response. In comparisons of 10-keV X-ray and Co-60 irradiations of Al-gate MOS capacitors at an oxide electric field of 1 MV/cm, predictions and experiments agree to within better than 20% for oxide thicknesses ranging from 35 to 1060 nm. For capacitors with TaSi/Al gates, they agree to within better than 30% at 1 MV/cm, with the largest differences occurring for 35-nm gate oxides. At other electric fields, the disagreement between experiment and prediction increases significantly for both Al- and TaSi/Al-gate capacitors. For medium-energy ( approximately 100-keV average photon energy) X-irradiations, the enhanced device response exhibits a much stronger dependence on endpoint bremsstrahlung energy than expected from TIGERP or CEPXS/ONETRAN simulations. Implications for hardness assurance testing are discussed. >

Charge collection in SOI capacitors and circuits and its effect on SEU hardness

Focused ion microbeam and broadbeam heavy-ion experiments on capacitors and SRAMs are used to investigate increased saturation upset cross sections recently observed in some silicon-on-insulator (SOI) integrated circuits (ICs). Experiments performed on capacitors show a very strong bias and oxide thickness dependence for charge collection. In combination with three-dimensional (3-D) simulations, these data suggest that the mechanism for charge collection in capacitors is due to perturbation of the substrate electric fields by charge deposition in the substrate. For substrates biased in depletion, these perturbations induce displacement currents through the oxide. Charge collection by displacement currents can be substantially reduced or mitigated by using heavily doped substrates. Experiments performed on SRAMs also show enhanced charge collection from displacement currents. However, experimental data and 3-D simulations show that for SRAMs, a second mechanism also contributes to charge collection. The 3-D simulations suggest that the charge collection results from drain and body-tie heavy-ion strikes within a few tenths of a micron of the body-to-drain junctions. These charge collection mechanisms can substantially reduce the SEU hardness and soft-error reliability of commercial SOI ICs.

Single-event upset and snapback in silicon-on-insulator devices and integrated circuits

The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

BUSFET-a radiation-hardened SOI transistor

The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are 1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or 2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. We call this structure the BUSFET-Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source.

Use of diffracted light from latent images to improve lithography control

As the microelectronics industry strives to achieve smaller device design geometries, control of linewidth, or critical dimension (CD), becomes increasingly important. Currently, CD uniformity is controlled by exposing large numbers of samples for a fixed exposure time which is determined in advance by calibration techniques. This type of control does not accommodate variations in optical properties of the wafers that may occur during manufacturing. In this work, a relationship is demonstrated between the intensity of light diffracted from a latent image consisting of a periodic pattern in the undeveloped photoresist and the amount of energy absorbed by the resist material (the exposure dose). This relationship is used to simulate exposure control of photoresist on surfaces having slight variations in optical properties, representative of those found in operating process lines. We demonstrate that linewidth uniformity of the developed photoresist can be greatly improved when the intensity of diffracted li...

Correlation between Co-60 and X-ray radiation-induced charge buildup in silicon-on-insulator buried oxides

Large differences in charge buildup in SOI buried oxides are observed for X-ray and Co-60 irradiations of SIMOX and Unibond transistors. The Co-60 response is typically worse than the X-ray response. These results are consistent with expectations derived from previous work on the relative charge yield versus field in thick oxides. The effects of bias configuration and substrate type on charge buildup and hardness assurance issues are explored via experiments and simulation. The worst-case bias condition is found to be either the off-state or transmission gate configuration. Simulations of the buried oxide electric field in the various bias configurations are used to illustrate the factors that affect charge transport and trapping in the buried oxides. Hardness assurance implications are discussed.

Optimum laboratory radiation source for hardness assurance testing

Silicon-on-insulator (SOI) and bulk-silicon transistors were irradiated using X-ray, Co-60 gamma, and proton radiation sources. Co-60 gamma irradiation generates larger radiation-induced threshold voltage shifts (by a factor of two) in SOI buried oxides and in parasitic field oxides under low-field conditions than X-ray or proton irradiation. For all devices examined, the radiation-induced threshold voltage shifts generated by X-ray irradiation were equal to, within experimental uncertainty, the radiation-induced threshold voltage shifts generated by proton irradiation. The differences in threshold voltage shifts for the different radiation sources are attributed to differences in stopping power and consequently charge yield. The results suggest that for simulating proton-rich space environments, X-ray laboratory radiation sources are better suited for hardness assurance testing than Co-60 gamma radiation sources. Using Co-60 gamma sources for hardness assurance testing will result in more conservative estimates of device failure levels. Thus, our results do not preclude the use of Co-60 gamma radiation sources for hardness assurance testing for proton-rich environments. For electron-rich space environments, Co-60 gamma radiation sources may be better suited for hardness assurance testing.