Sehat Sutardja

1.2 The future of IC design innovation

One of the greatest achievements of human kind is undoubtedly its ability to build tiny machines that marry the functionalities of computers and wireless communication devices so cheaply that almost anyone in the world can afford them. Every one of us carries, at least, one such device in our pocket, yet we rarely think how in the world anyone could have created such a thing! Even the experts in our industry could not have predicted that this would have happened so quickly. What we have achieved in the course of the design and implementation of these sophisticated systems could be considered nothing short of a miracle, considering that billions of transistors have to work together flawlessly. (Well, sort of!) The reality is that some of these devices are now so complex that we need thousands of engineers to design, validate, and support them, including recovery from inefficiencies and bugs along the way. But, despite their ever-increasing complexity, the way we build these devices has not changed much over the past decades. Integrated-circuit (IC) design engineers blindly do what they are told - integrate as much functionality into a single device, believing that more is better! This more-the-better mentality is not surprising because we saw in the past that the more completely we integrate the cheaper things become. However, the cost and complexity of building billions of transistors on a single device is finally taking a toll on our engineers, which calls for new paradigm shifts in designing complex devices. If chip-design engineers had considered the financial optimization of the overall design process, they would have built things differently. They would have realized that certain functions are better grouped into highly specialized integrated circuits that easily and seamlessly talk to each other without compromising the overall system cost and performance. The key to making this happen is what I call the Lego-Block approach of designing integrated circuits. However, in order for the Lego-Block approach to materialize, we need to change the way we architect our devices. For example, we need to define a new chip-to-chip interconnect protocol, take advantage of multi-chip-module packaging and high-speed SerDes technology, redefine the memory hierarchy to take advantage of 3D solid-state memory instead of blindly increasing the DRAM size, repartition DRAM to serve different logical functions instead of building gigantic single-die DRAM to serve every function, change the way we build DRAM so that they are optimized more for performance and power efficiency instead of capacity, and redefine what should be done in hardware versus software. In short, we need to change our way of thinking, and be brave enough to reject common wisdom! If we fail to take action, soon we will no longer see cost savings. On the other hand, if we succeed, we will see life beyond the end of Moores Law!

A 0.55 nV//spl radic/(Hz) gigabit fully-differential CMOS preamplifier for MR/GMR read application

A low-noise Gb fully differential preamp in 0.25 /spl mu/m CMOS has a variable gain with constant 850 MHz bandwidth, and has a variable bandwidth with constant gain. Noise is <0.55 nV//spl radic/(Hz). The power consumption is 600 mW. The die of a 4-channel IC is <4.2 mm/sup 2/.

360 Mb/s (400 MHz) 1.1 W 0.35 /spl mu/m CMOS PRML read channels with 6 burst 8-20/spl times/ over-sampling digital servo

Rapid advances in giant magneto resistive (GMR) head technology will soon allow disk drive manufacturers to significantly increase both the linear and track density at the same time while maintaining acceptable error-rate performance. The steep increase in the linear density demands higher-performance and higher-data-rate partial response maximum likelihood (PRML) read channel electronics, while the increase in the track density demands higher-accuracy servo signal processing. A 360Mb/s CMOS partial response maximum likelihood (PRML) read channel for use in high-capacity low-power disk drive applications uses an industry-standard 0.35/spl mu/m one-poly-two-metal (1P2M) CMOS process technology.

Slowing of Moore's law signals the beginning of smart everything

After more than four decades of semiconductor revolution led by CMOS technology, the ability to shrink transistors by 50% every 18 to 24 months is finally coming to an end. For years, the end of transistor scaling, otherwise known as the end of Moores law, had been prematurely predicted. Case in point just as the industry thought that the fundamental optical wavelength limit would finally inhibit the progress of Moores law, wet lithography came to the rescue; giving us 40nm and then 28nm logic process nodes. Now however, in order to get even smaller transistors, we are finding out we need to replace the age old planar bulk transistors with Finfet. The industry will also need to use more expensive and time consuming multi patterning techniques starting with double patterning at the 16nm node and quad patterning at 10nm and at 7nm; drastically increasing the mask cost. As a result, after taking into account the mask costs, we can no longer have the fantastic cost reductions of the past from device scaling. Therefore from an economic point of view, the beginning of the end of Moores law is now upon us.