Jin-Yuan Lee

SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof

Using an extra boron implant to improve the NMOS reverse narrow width effect in shallow trench isolation process

Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer

Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell

Modified BP-TEOS tungsten-plug contact process

Self-aligned contact structures using high selectivity etching

Modified tungsten-plug contact process

Static random access memory design and fabrication process featuring dual self-aligned contact structures

Method of making polysilicon-via structure for four transistor, triple polysilicon layer SRAM cell including two polysilicon layer load resistor

Method for reducing the contact resistance of a butt contact