Kazuhiko Kajigaya

A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier

The authors present two developments for DRAM voltage limiters: a precise internal-voltage generator composed of a PMOS threshold-voltage-difference generator and a tunable voltage-up converter with fuse trimming; and a stabilized driver composed of a feedback amplifier with compensation for a time-dependent load. These circuits provide a voltage not susceptible to the supply-voltage and substrate-voltage bouncings, temperature variation, and threshold-voltage deviation due to the process fluctuation, while maintaining CMOS-DRAM process compatibility. Moreover, feedback-loop stability and frequency response are maintained by ensuring a phase margin of 55° at a unity-gain frequency of 10 MHz using compensation through zero insertion. Implementation of these new circuits in a 16-Mb CMOS DRAM is reported

A 29-ns 64-Mb DRAM with hierarchical array architecture

A 29-ns (RAS access time), 64-Mb DRAM with hierarchical array architecture has been developed. For consistent high yields and high speed, a CMOS segment driver circuit is used as a hierarchical word line scheme. To achieve high speed, precharge signal (PC) drivers for equalizing the bit lines pairs, and shared sense amplifier signal (SHR) drivers are distributed in the array. To enhance sense amplifiers speed in low array voltage, an over driven sense amplifier is adopted. A hierarchical I/O scheme with semidirect sensing switch is introduced for high speed data transfer in the I/O paths. By combining these proposed circuit techniques and 0.25-/spl mu/m CMOS process technologies with phase-shift optical lithography, an experimental 64-Mb DRAM has been designed and fabricated. The memory cell size is 0.71/spl times/1.20 /spl mu/m/sup 2/, and the chip size is 15.91/spl times/9.06 mm/sup 2/. A typical access time under 3.3 V power supply voltage is 29 ns.

A multi-gigabit DRAM technology with 6F/sup 2/ open-bit-line cell distributed over-driven sensing and stacked-flash fuse

To cope with difficult device miniaturization in the multi-gigabit era, memory cells smaller than the traditional 8F/sup 2/ folded bitline (BL) cell are needed. A 6F/sup 2/ trench capacitor folded-BL cell has been recently described. However, it needs not only additional tight-pitch layers to create a vertically folded-BL arrangement, but also a vertical transistor. The 6F/sup 2/ open-BL cell enabling a simple planar transistor is another candidate as its inherently large imbalance noise between pairs of BLs is reduced. Low-voltage, high-speed array operation is essential in the multi-gigabit era. A conventional non-over-driven sensing scheme cannot achieve a high enough speed at an array voltage below 1.6 V, because the threshold voltage (Vth) cannot be reduced <0.1 V to obtain a low enough stand-by current. Distributed over-driven sensing enables a higher speed due to reduced voltage loss caused by distributed drivers combined with meshed power lines. Consequently, compared with the conventional schemes, the sensing time for a 1.2 V array voltage necessary for the 1 Gb generation decreased by 6.9 ns and 2.0 ns. Hence, this sensing scheme is promising for array voltages below 1.0 V in multi-gigabit memory. In multi-gigabit DRAMs, redundancy for degraded cells after packaging is a major concern. To overcome this a scheme is adopted which features a stacked flash fuse composed of three series flash fuses utilizing standard CMOS transistors without any additional process steps. Thus this technology can be used to fabricate a 0.13 μm 180 mm/sup 2/ 1 Gb DRAM assembled in a 400-mil package.

A low-impedance open-bitline array for multigigabit DRAM

The noise-generating mechanisms inherent in the open-bitline DRAM array using the 6F/sup 2/ (F: feature size) memory cells and techniques for reducing the noise are described. The sources of differential noise coupled to the paired bitlines laid out in two arrays are the p-well, cell plate, and the group of nonselected wordlines. It was found, by simulation and by experiment with a 0.13-/spl mu/m 256-Mb test chip, that the level of noise is dramatically reduced by using a low-impedance array with careful layout featuring low-resistivity materials, tight bridging between pairs of adjacent arrays, and a small array, achieving a comparable level of noise to that seen in the twisted and folded-bitline array. On basis of these results, it turns out that the open-bitline array has a strong chance of revival in the multigigabit generation, as long as these noise reduction techniques are applied.

Dual-Regulator Dual-Decoding-Trimmer DRAM Voltage Limiter For Burn-in Test

This paper presents a DRAM voltage limiter with a burn-in test mode. It features a dual-regulator dual-trimmer scheme that provides a precise stress voltage in a burn-in test while maintaining a constant limited voltage under normal operation. A regulator is used to preserve a constant difference between the internal burn-in voltage and the supply voltage. Two sets of trimmers reduce the voltage deviations of both the vss burn-in and normal-operation voltages within k 0.13 V. The proposed circuits are implemented in a 16-Mb CMOS DRAM. A up to 120°C is obtained by simply elevating the supply voltage to 8 V as in the conventional burn-in procedures. burn-in voltage regulated to f 50 mV at an ambient temperature = kZVN VL: Voltage limiter LI: DRAM core Lz: I/O circuitry B: Burn-in operating point N: Normal operating point

Dual-regulator dual-decoding-trimmer DRAM voltage limiter for burn-in test

The authors present a dynamic RAM (DRAM) voltage limiter with a burn-in test mode. It features a dual-regulator dual-trimmer scheme that provides a precise stress voltage in a burn-in test while maintaining a constant limited voltage under normal operation. A regulator is used to preserve a constant difference between the internal burn-in voltage and the supply voltage. Two sets of trimmers reduce the voltage deviations of both the burn-in and normal-operation voltages within +or-0.13 V. The circuits are implemented in a 16-Mb CMOS DRAM. A burn-in voltage regulated to +or-50 mV at an ambient temperature up to 120 degrees C is obtained simply by elevating the supply voltage to 8 V as in conventional burn-in procedures. >

A dynamic CAM - based on a one-hot-spot block code - for millions-entry lookup

With the aim of realizing large-scale and low-power CAMs for millions-entry lookup, the authors have devised a one-hot-spot block code and developed three circuit techniques. The proposed code efficiently stores IP addresses and reduces the entry count down by 52% on average. The first and second techniques, a hierarchical match-line structure and an on-chip entry compression/extraction scheme, enable the proposed code to be applied to our new CAM. In addition to the second technique, the third technique, a search-depth control scheme, restricts activating unneeded search lines and reduces power consumption down by 45%. In the case of 72-bit data, the proposed CAM, using a stacked capacitor, effectively achieves 1.5 million entries, which is six times larger than that of a conventional static TCAM.

Concordant memory design using statistical integration for the billions-transistor era

An embedded DRAM macro in a logic compatible 90nm CMOS process is designed with low-noise core architecture and high-accuracy post-fabrication tuning. With a 5fF/cell capacitance, a 61% improvement of sensing accuracy enables 322MHz random-cycle operation and reduces data retention power to 60 /spl mu/W.

A 255 Mb SDRAM with subthreshold leakage current suppression

A 204.9 mm/sup 2/ 256 Mb SDRAM has a 29 ns RAS access time and a 1ns clock access time. The SDRAM enables double-data-rate (DDR) at more than 300 Mb/s/pin, and features low-Vth and high-drivability MOSFETs combined with subthreshold leakage current suppression that reduces standby current to 200 /spl mu/A. A 64-cycle lock-in 0.1 ns resolution delay-locked-loop (DLL) is used.

Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation

A DRAM-cell array with 12-F 2 twin cell was developed and evaluated in terms of speed, retention time, and low-voltage operation. The write and read-out times of the twin-cell array are shorter than those of a single-cell array by 70% and 40% respectively, because of parallel writing and reading of half charge to and from two memory cells. According to measured retention characteristics of the single cells, the twin-cell array improves retention time by 20% compared with the single-cell array at 1V and keeps the retention time of the single-cell array at 0.4 V. Furthermore, the cell accepts the plate-driven scheme without the need of a dummy cell, lowering the necessary word-line voltage by 0.4 V.