Seiki Goto

The efficiency of class-F and inverse class-F amplifiers

The efficiency of class-F and inverse class-F amplifiers are studied using measurements and theories. At high quiescent current, inverse class-F amplifiers show higher efficiency than that of class-F. This phenomenon is experimentally ensured with GaAs pHEMTs and GaAs HBTs. A harmonic balanced simulation also supports this result, and reveals the difference between the classes. An analytic waveform analysis with restricted harmonics explains this dependence on the quiescent currents.

A high power density TaN/Au T-gate pHEMT with high humidity resistance for Ka-Band applications

A 0.8 W/mm high power pHEMT with high humidity resistance is reported. By using tantalum nitride as the refractory gate metal and a silicon nitride layer prepared by a catalytic chemical vapor deposition technique for passivation of this transistor, tough moisture resistance was obtained showing no Id degradation even after 500 hours at 130 degrees centigrade and 85% humidity. Moreover, the Schottky breakdown voltage of the TaN gate is higher than that of a WSiN gate. A one-stage prematched amplifier with the new pHEMT has achieved 0.83 W/mm output power at Vds = 8 V, with 8.5 dB gain and 40% power added efficiency in the Ka-band. These are some of the highest power figures ever reported.

A Low Distortion 25 W Class-F Power Amplifier Using Internally Harmonic Tuned FET Architecture for 3.5 GHz OFDM Applications

An ultra low distortion class-F power amplifier for base stations of broadband access systems is presented. This amplifier adopts internally harmonic tuned FET architecture (IHT-FET) to improve the linearity under class AB operating conditions. The feature of this architecture is an on-chip input 2nd harmonic tuning circuit placed in front of each FET unit cell to achieve accurate control of input 2nd harmonic impedance. With the proposed IHT-FET architecture, a single-chip multi-cell FET for verification exhibits a low distortion of a -51 dBc ACPR and a 19% PAE with a 11.8-dB associated gain at a 10-dB back-off output power level under a 3.5-GHz 3GPP W-CDMA signal test. This ACPR corresponds to a 10-dB reduction in ACPR of a conventional FET. In addition, a 25 W power amplifier with two IHT-FET chips successfully achieves a 1.5% EVM (error vector magnitude) at an output power of 34.6 dBm under a 3.5-GHz WiMAX (IEEE 802.16a) compliant OFDM signal test, where the output power is a 10-dB back-off level

A high efficiency, high voltage, balanced cascode FET

A high efficiency, high operating voltage GaAs HFET is presented. A balanced cascode circuit without RF feedback, which achieves the high PAE of 78.2% at 2.1GHz, is proposed. The optimization of a balance capacitor is analyzed theoretically and proved experimentally. This result contributes to the design of high voltage power amplifiers with low breakdown voltage transistors.

Stability analysis and layout design of an internally stabilized multi-finger FET for high-power base station amplifiers

A high-power, discrete, and internally-matched FET, such as for use in base station amplifiers, consists of lots of gate fingers to realize a very large periphery. It is well-known that many active devices combined in parallel likely form many closed loops and cause odd mode oscillation. However, stability analysis among FET fingers is usually complex, because of the existence of lots of active nodes. In this paper, novel internally stabilized multi-finger FET layout methodology with a branched gate feed structure is proposed, to stabilize among gate fingers without increasing the occupied layout area of the FET. The feature of this layout is that the branched gate feed structure, which can be fabricated without any extra processing step, functions as a resistor to isolate each FET cell. Stability analysis and layout design were achieved by using the NDF (Normalized Determinant Function) evaluation technique, which can deal with lots of active nodes. In an experiment for a GaAs FET of 134 mm gate width with 168 gate fingers, this stability analysis precisely predicted an oscillation frequency of the FET having multiple closed loops. The new approach presented here on the gate feed structure effectively suppressed odd mode oscillation.

A V-Band High Power and High Gain Amplifier MMIC using GaAs PHEMT Technology

We report the performance of a V-band 5-stage high power amplifier MMIC using a millimeter-wave 0.1 mum GaAs pHEMT. It has demonstrated that an output power of 28.8 dBm (759 mW) at 1 dB compression point with 17.8 dB power gain and 14.2% PAE at 59 GHz. And it delivers an output power of 28.9 dBm (776 mW) at a saturation point. These results represent, to the best of our knowledge, the highest output power and power gain for single-ended MMICs.

A Low 1/f Noise and High Reliability InP/GaAsSb DHBT for 76 GHz Automotive Radars

To develop a low 1/f noise and high reliability InP/GaAsSb DHBT, experimental analyses on the recombination current have been carried out. The results show that the recombination current that can affect 1/f noise and reliability originates from the surface of the base. We have optimized the ledge and passivation film on the base surface of InP/GaAsSb DHBT. The optimized DHBT offers 7 dB lower 1/f noise level than the non-optimized DHBT. Additionally, in the high temperature burn-in test, no degradation has been induced even after 1,000 hr. It can satisfy the criterion of automotive radars. The W-band oscillator with the optimized DHBT delivers a remarkably low phase noise of -107 dBc/Hz at 1MHz-offset. This phase noise is 10 dB lower than that of the non-optimized HBT oscillator. These results experimentally confirm that decreasing 1/f noise is effective for the design of a low phase noise oscillator using InP/GaAsSb DHBT. To our knowledge, this is the first report to reveal that the base surface structure of InP/GaAsSb DHBT is a key factor in the improvement of reliability and phase noise.

Intermodulation distortion analysis of class-F and inverse class-F HBT amplifiers

The third-order intermodulation distortions (IM3s) of class-F and inverse class-F heterojunction bipolar transistor amplifiers were compared experimentally. It was revealed that the IM3 of inverse class F is lower than that of class F at high input power (P/sub in/), although the better class for IM3 at low P/sub in/ changes from class F to inverse class F according to the increase of the quiescent current (I/sub q/). The different IM3 behaviors are mainly caused by the different gain variations in both amplifiers. At a low P/sub in/, the gain of class F is larger than that of inverse class F. The larger gain in class F causes a gradual gain decrease and a steep gain rise at high and low I/sub q/, respectively. On the other hand, the gain of inverse class F is larger than that of class F at a high P/sub in/. The larger gain in inverse class F causes a gradual gain decrease at all I/sub q/ values. These gradual gain decreases are one of main causes of a lower IM3. These phenomena can be explained by the output current (I/sub out/) and voltage (V/sub out/) waveforms, which differ according to the harmonic loads. The I/sub out/ and V/sub out/ positive half-sinusoidal waveforms, which consist of in-phase second harmonics, are effective for large-gain operations. The positive half-sinusoidal I/sub out/ waveform of the class-F amplifier prevents a gain decrease at a low P/sub in/ and high I/sub q/, and the similar V/sub out/ waveform in inverse class F prevents a gain decrease at a high P/sub in/.

A Nonlinear Drain Resistance pHEMT model for Millimeter-wave High Power Amplifiers

A high power pHEMT with longer drain-gate separation can operate at higher voltage. However, it shows large output power loss at millimeter-wave in addition to the conventional parasitic power dissipation. The nonlinear drain resistance Rd of the pHEMT is found to cause the large power loss, although it behaves as a conventional resistor at low frequency. The nonlinearity of the Rd is modeled and shows good agreement with the measurement. Comparisons of pHEMTs with different nonlinear Rd also support the model.

An 11 W Ku-band heterostructure FET with WSi/Au T-shaped gate

We developed a heterostructure FET (HFET) with a high output power and a high power-added efficiency (PAE) at Ku-band. 8 W and 11.2 W output powers were obtained with power-added efficiencies of 48% and 41% and linear gains of 9 dB and 8.6 dB at 12 GHz, respectively. This is the highest power and efficiency ever reported which is achieved by a single FET chip at this frequency.<<ETX>>