Tetsuo Kunii

K-band high gain and high reliability GaAs power FET with sub-half micron WSi/Au T-shaped gate

We have developed a K-band GaAs power MESFET with 0.35 /spl mu/m WSi/Au T-shaped gate structure. This structure has been realized by forming a SiO/sub 2/ sidewall at both sides of recess, so the gate length is easily reduced to sub-half micron. A gate-to-drain breakdown voltage (Vgdo) of over 15 V, which depends strongly on the distance between gate edge and recess edge, is achieved when the sidewall width is adjusted to be more than 0.25 /spl mu/m. The 900 /spl mu/m gate-width FET has delivered an output power at 1 dB gain-compression point of 27.2 dBm with a linear gain of 9.5 dB at 18 GHz. An excellent mean time to failure (MTTF) of over 3E7 hours at Tch=125/spl deg/C has been obtained for the WSi/Au gate FET.

A high power density TaN/Au T-gate pHEMT with high humidity resistance for Ka-Band applications

A 0.8 W/mm high power pHEMT with high humidity resistance is reported. By using tantalum nitride as the refractory gate metal and a silicon nitride layer prepared by a catalytic chemical vapor deposition technique for passivation of this transistor, tough moisture resistance was obtained showing no Id degradation even after 500 hours at 130 degrees centigrade and 85% humidity. Moreover, the Schottky breakdown voltage of the TaN gate is higher than that of a WSiN gate. A one-stage prematched amplifier with the new pHEMT has achieved 0.83 W/mm output power at Vds = 8 V, with 8.5 dB gain and 40% power added efficiency in the Ka-band. These are some of the highest power figures ever reported.

A high reliability GaN HEMT with SiN passivation by Cat-CVD

This is the first report of catalytic vapor deposition (Cat-CVD) passivated AlGaN/GaN HEMT. We have found out that the Cat-CVD passivation film with NH3 treatment greatly enhances the reliability of the AlGaN/GaN HEMT. It is rationalized, through the low frequency capacitance-voltage measurement, that the NH3 treatment in the Cat-CVD reactor before the SiN film deposition minimizes the damage at the SiN/AlGaN interface, leading to reducing the surface trap density. The AlGaN/GaN HEMT passivated by the Cat-CVD SiN film suppresses the degradation of an output power to less than 0.4 dB under the RF operation of Vd = 30 V, f = 5 GHz after 200 h.

High gain and high efficiency K-band power HEMT with WSi/Au T-shaped gate

We have developed WSi/Au T-shaped buried gate pseudomorphic HEMT with the good uniformity of recess current by using a selective etching process and with a high off-state break down voltage of over 19 V. A 1.4 W output power has been obtained with a power-added efficiency of 55.6% and an associated gain of 9.2 dB under high voltage operation of Vd=10 V at 18 GHz. This is the highest gain and efficiency achieved by a single FET chip with over a watt output power at this frequency.

A Low Distortion 25 W Class-F Power Amplifier Using Internally Harmonic Tuned FET Architecture for 3.5 GHz OFDM Applications

An ultra low distortion class-F power amplifier for base stations of broadband access systems is presented. This amplifier adopts internally harmonic tuned FET architecture (IHT-FET) to improve the linearity under class AB operating conditions. The feature of this architecture is an on-chip input 2nd harmonic tuning circuit placed in front of each FET unit cell to achieve accurate control of input 2nd harmonic impedance. With the proposed IHT-FET architecture, a single-chip multi-cell FET for verification exhibits a low distortion of a -51 dBc ACPR and a 19% PAE with a 11.8-dB associated gain at a 10-dB back-off output power level under a 3.5-GHz 3GPP W-CDMA signal test. This ACPR corresponds to a 10-dB reduction in ACPR of a conventional FET. In addition, a 25 W power amplifier with two IHT-FET chips successfully achieves a 1.5% EVM (error vector magnitude) at an output power of 34.6 dBm under a 3.5-GHz WiMAX (IEEE 802.16a) compliant OFDM signal test, where the output power is a 10-dB back-off level

A high efficiency, high voltage, balanced cascode FET

A high efficiency, high operating voltage GaAs HFET is presented. A balanced cascode circuit without RF feedback, which achieves the high PAE of 78.2% at 2.1GHz, is proposed. The optimization of a balance capacitor is analyzed theoretically and proved experimentally. This result contributes to the design of high voltage power amplifiers with low breakdown voltage transistors.

Stability analysis and layout design of an internally stabilized multi-finger FET for high-power base station amplifiers

A high-power, discrete, and internally-matched FET, such as for use in base station amplifiers, consists of lots of gate fingers to realize a very large periphery. It is well-known that many active devices combined in parallel likely form many closed loops and cause odd mode oscillation. However, stability analysis among FET fingers is usually complex, because of the existence of lots of active nodes. In this paper, novel internally stabilized multi-finger FET layout methodology with a branched gate feed structure is proposed, to stabilize among gate fingers without increasing the occupied layout area of the FET. The feature of this layout is that the branched gate feed structure, which can be fabricated without any extra processing step, functions as a resistor to isolate each FET cell. Stability analysis and layout design were achieved by using the NDF (Normalized Determinant Function) evaluation technique, which can deal with lots of active nodes. In an experiment for a GaAs FET of 134 mm gate width with 168 gate fingers, this stability analysis precisely predicted an oscillation frequency of the FET having multiple closed loops. The new approach presented here on the gate feed structure effectively suppressed odd mode oscillation.

A high power density and high efficiency UHF-band HFET for low voltage operation

A high power density and high efficiency AlGaAs-GaAs Heterostructure FET (HFET) for 0.9 GHz digital cellular phone systems has been successfully developed. The device has delivered a high power density of 117 mW/mm with a power-added efficiency (PAE) of 37.6% with a low adjacent channel power (ACP) of -53.4 dBc at a low drain bias of 3.3 V at 950 MHz operating frequency.<<ETX>>

Drain current drift by holes trapped in Schottky contact in WSi gate GaAs MESFETs

Hysteretic drain current (Id) drift phenomena observed in the high power operation of WSi gate GaAs MESFETs were studied. The existence of a thin insulating layer at WSi-GaAs interface originated by the native oxide on GaAs surface was revealed by XPS and X-ray reflection. Id drift phenomena can be explained as the effect of holes being trapped in the insulating layer at the WSi-GaAs Schottky contact interface.

An 11 W Ku-band heterostructure FET with WSi/Au T-shaped gate

We developed a heterostructure FET (HFET) with a high output power and a high power-added efficiency (PAE) at Ku-band. 8 W and 11.2 W output powers were obtained with power-added efficiencies of 48% and 41% and linear gains of 9 dB and 8.6 dB at 12 GHz, respectively. This is the highest power and efficiency ever reported which is achieved by a single FET chip at this frequency.<<ETX>>