Tomoki Oku

Super low-noise self-aligned gate GaAs MESFET with noise figure of 0.87 dB at 12 GHz

An advanced self-aligned multilayer gate FET (SAMFET) has been developed for super-low-noise monolithic microwave integrated circuit (MMIC) amplifiers. Reduction of gate resistance by adopting a novel T-shaped multilayer gate results in a 0.2-dB improvement of the minimum noise figure compared with conventional SAMFETs. At 12-GHz, the advanced SAMFET gives a minimum noise figure of 0.87 dB with associated gain of 10.62 dB. Excellent uniformity of performance and high reliability are confirmed. They are attributed to a complete planar structure and refractory WSi gate contact. This technology is considered promising for high-performance, low-cost MMICs.<<ETX>>

A 38/77 GHz MMIC transmitter chip set for automotive applications

This paper describes the successful development of 38/77 GHz transmit MMICs for automotive applications. They consist of a 38 GHz amplifier, a frequency doubler, and a 77 GHz power amplifier. These amplifiers achieve output powers of 16 dBm at 38 GHz and 15 dBm at 76.5 GHz at 1 dB gain compression point. The output power of the 77 GHz amplifier is one of the highest delivered by a single chip MMIC at 76.5 GHz. The frequency doubler delivers an output power of 5.7 dBm at 76.5 GHz. These results are promising for automotive applications in the W-band.

K-band high gain and high reliability GaAs power FET with sub-half micron WSi/Au T-shaped gate

We have developed a K-band GaAs power MESFET with 0.35 /spl mu/m WSi/Au T-shaped gate structure. This structure has been realized by forming a SiO/sub 2/ sidewall at both sides of recess, so the gate length is easily reduced to sub-half micron. A gate-to-drain breakdown voltage (Vgdo) of over 15 V, which depends strongly on the distance between gate edge and recess edge, is achieved when the sidewall width is adjusted to be more than 0.25 /spl mu/m. The 900 /spl mu/m gate-width FET has delivered an output power at 1 dB gain-compression point of 27.2 dBm with a linear gain of 9.5 dB at 18 GHz. An excellent mean time to failure (MTTF) of over 3E7 hours at Tch=125/spl deg/C has been obtained for the WSi/Au gate FET.

A W-band ultra low noise amplifier MMIC using GaAs pHEMT

This paper presents a newly developed 76 GHz three-stage LNA for automotive radar systems. The LNA utilizes multi band rejection filter type stabilizing circuits to achieve good noise figure together with good stability. The operating bias condition was carefully chosen to obtain low temperature dependence of gain. As a result, the LNA delivers a noise figure of 3.5 dB typically, small temperature dependence of gain of -0.016 dB/deg.C and high return loss using a highly conventional 0.19 /spl mu/m T-shaped gate AlGaAs/InGaAs/GaAs pHEMT process.

A high power density TaN/Au T-gate pHEMT with high humidity resistance for Ka-Band applications

A 0.8 W/mm high power pHEMT with high humidity resistance is reported. By using tantalum nitride as the refractory gate metal and a silicon nitride layer prepared by a catalytic chemical vapor deposition technique for passivation of this transistor, tough moisture resistance was obtained showing no Id degradation even after 500 hours at 130 degrees centigrade and 85% humidity. Moreover, the Schottky breakdown voltage of the TaN gate is higher than that of a WSiN gate. A one-stage prematched amplifier with the new pHEMT has achieved 0.83 W/mm output power at Vds = 8 V, with 8.5 dB gain and 40% power added efficiency in the Ka-band. These are some of the highest power figures ever reported.

A high reliability GaN HEMT with SiN passivation by Cat-CVD

This is the first report of catalytic vapor deposition (Cat-CVD) passivated AlGaN/GaN HEMT. We have found out that the Cat-CVD passivation film with NH3 treatment greatly enhances the reliability of the AlGaN/GaN HEMT. It is rationalized, through the low frequency capacitance-voltage measurement, that the NH3 treatment in the Cat-CVD reactor before the SiN film deposition minimizes the damage at the SiN/AlGaN interface, leading to reducing the surface trap density. The AlGaN/GaN HEMT passivated by the Cat-CVD SiN film suppresses the degradation of an output power to less than 0.4 dB under the RF operation of Vd = 30 V, f = 5 GHz after 200 h.

A V-Band High Power and High Gain Amplifier MMIC using GaAs PHEMT Technology

We report the performance of a V-band 5-stage high power amplifier MMIC using a millimeter-wave 0.1 mum GaAs pHEMT. It has demonstrated that an output power of 28.8 dBm (759 mW) at 1 dB compression point with 17.8 dB power gain and 14.2% PAE at 59 GHz. And it delivers an output power of 28.9 dBm (776 mW) at a saturation point. These results represent, to the best of our knowledge, the highest output power and power gain for single-ended MMICs.

Mechanism for Desorption of SiF4 from an SiO2 Film Surface in HF Solutions

An extended Huckel calculation was employed to calculate the change in the electron density on the Si-O back bonds and the total electronic energy during the reaction at the SiO2 film surface. We demonstrate that the desorption of SiF4 occurs as follows: (1) bifluoride (HF - 2 ) ions dissociate into HF monomers and F- ions near the surface, (2) F- ions attack the -SiF3 surfaces and hydrogen ions attack the oxygen atoms of the back bond, (3) the O-Si-F bond angle decreases and the Si-O bond strength is weakened, (4) the hydrogen atoms passivate the oxygen atoms after tetrahedral SiF4 molecules are generated and the Si-O back bonds are broken. The evaluated activation energy of the desorption of SiF4 is 0.8eV.

Drain current drift by holes trapped in Schottky contact in WSi gate GaAs MESFETs

Hysteretic drain current (Id) drift phenomena observed in the high power operation of WSi gate GaAs MESFETs were studied. The existence of a thin insulating layer at WSi-GaAs interface originated by the native oxide on GaAs surface was revealed by XPS and X-ray reflection. Id drift phenomena can be explained as the effect of holes being trapped in the insulating layer at the WSi-GaAs Schottky contact interface.

A high-speed 16-kb GaAs SRAM of less than 5 ns using triple-level metal interconnection

The authors have realized 16-kb SRAMs with maximum address access time of less than 5 ns and typical power dissipation of less than 2 W at temperatures ranging from 25 degrees C to 100 degrees C. For the RAMs, they have developed a triple-level Au-based interconnection technology that reduces the wiring length and chip size of the SRAM so as to achieve high speed and high yield. Consequently, the wiring length and chip size are reduced to 69% and 58%, respectively, of those obtained by in previous work. The authors experimentally compared the delay time incurred by double-level interconnection and that by triple-level interconnection. This ratio is found to agree well with the simulated one by a model with distributed RC delay. After successfully suppressing Au hillock generation by lowering the process temperature, yield per wafer of 10% is obtained. >