Seitaro Kawai

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding

This paper presents a 64-QAM 60GHz CMOS transceiver, which achieves a TX-to-RX EVM of -26.3dB and can transmit 10.56Gb/s in all four channels defined in IEEE802.11ad/WiGig. By using a 4-bonded channel, 28.16Gb/s can be transmitted in 16QAM. The front-end consumes 251mW and 220mW from a 1.2-V supply in transmitting and receiving mode, respectively. Figure 20.3.1 shows the 60GHz direct-conversion front-end design. The transmitter consists of a 6-stage PA, differential preamplifiers, I/Q passive mixers and a quadrature injection-locked oscillator (QILO). The receiver consists of a 4-stage LNA, differential amplifiers, I/Q double-balanced mixers, a QILO, and baseband amplifiers. A direct-conversion architecture is employed for both TX and RX because of wide-bandwidth capability [1]. The LO consists of the 60GHz QILO and a 20GHz PLL. The 60GHz QILO works as a frequency tripler with the integrated 20GHz PLL. It can generate 7 carrier frequencies with a 36/40MHz reference, 58.32GHz(ch.1), 60.48GHz(ch.2), 62.64GHz(ch.3), and 64.80GHz(ch.4) defined in IEEE802.11ad/WiGig, 59.40GHz(ch.1-2), 61.56GHz(ch.2-3), and 63.72GHz(ch.3-4) for the channel bonding.

A digitally-calibrated 20-Gb/s 60-GHz direct-conversion transceiver in 65-nm CMOS

This paper presents a digitally-calibrated 60-GHz direct-conversion transceiver. To improve the error vector magnitude (EVM) performance over the wide bandwidth, a digital calibration technique is applied. The 60-GHz transceiver implemented by 65 nm CMOS achieves the maximum data rates of 20 Gb/s in 16QAM mode. The transmitter and receiver consume 351 mW and 238 mW from 1.2 V supply, respectively. As a 60-GHz transceiver, the best Tx-to-Rx EVM performance of -26.2 dB is achieved for 16QAM 7Gb/s data rate.

13.3 A 56Gb/s W-band CMOS wireless transceiver

This paper presents a 56Gb/s 16-QAM 65nm CMOS transceiver using a W-band carrier. Two wideband IF signals are up- and downconverted simultaneously with 68GHz and 102GHz carriers. The transceiver achieves 56Gb/s data-rate with TX-to-RX EVM of -16.5dB within 0.1m distance. The transceiver consumes 260mW and 300mW from a 1V supply in TX and RX modes, respectively. This results in 10pJ/bit efficiency, which is a state-of-the-art-efficient high-data-rate mm-Wave CMOS transceiver.

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay

It is predicted that the required wireless communication capacity will become 1000 times higher every 10 years. Many wireless standards are under discussion to satisfy the unprecedented capacity requirement. For example, the IEEE802.11ay standard is targeting over 100Gb/s data-rate by using the 60GHz band. Unfortunately, the channel bandwidth of 2.16GHz for the 60GHz band is not wide enough to realize such a high data-rate, so a channel-bonding capability is strongly demanded to extend the data-rate as well as 64-QAM support, achieving 42.24Gb/s. To realize 4-channel bonding operation with 64QAM, fine and wideband I/Q mismatch calibration is one of the remaining issues. In addition, an 8b 14.08GS/s ADC is required to support 42.24Gb/s, which is usually realized by a massive time-interleaved ADC, and needs unreasonably large power consumption. In this work, a frequency-interleaved (FI) architecture is employed for the 60GHz transceiver-side to mitigate the wideband I/Q mismatch issue and the ADC requirement. In addition, an asymmetric quadrature injection-locked oscillator (QILO) is proposed to widen the locking range.

19.5 An HCI-healing 60GHz CMOS transceiver

The research of 60GHz CMOS transceivers has bloomed due to their capability of achieving low-cost multi-Gb/s short-range wireless communications [1]. Considering practical use of the 60GHz CMOS transceivers, longer operation lifetime with high output power is preferred to provide reliable products. Unfortunately, as indicated in [2], the output power capability of the transmitter will gradually degrade due to the hot-carrier-injection (HCI) effects in the standard CMOS transistors at large-signal operation (e.g. power amplifiers). It is because the inherently large voltage swing at the output of the power amplifiers (PAs) is the main source of the HCI damage. Unfortunately, a thick-oxide transistor, a common solution for reliability issues at lower frequencies, cannot be utilized for 60GHz CMOS PA design due to its limited maximum oscillation frequency (fmax).

L-2L de-embedding method with double-T-type PAD model for millimeter-wave amplifier design

For millimeter-wave CMOS circuit design, accurate device models are necessary. Especially an accurate de-embedding method is very important. Hence, precise deembedding of pad parasitics is the first and valuable step to achieve accurate device models. In this work, a new pad modeling based on an L-2L de-embedding is proposed. The pad model is derived with an assumption that characteristic impedance of transmission line becomes constant at high frequency. Every device used in an amplifier is characterized with the proposed de-embedding method, and simulation and measurement results well agree with each other up to 110 GHz.

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation

A low-power and small-area 60-GHz CMOS transmitter with oscillator pulling mitigation is presented. The subharmonic injection locking technique for the suppression of pulling effects is analyzed and demonstrated. The transmitter fabricated in a 65nm CMOS process achieves 7.04-Gb/s data rate with an EVM performance of −25 dB in 16QAM. The whole transmitter consumes 210 mW from a 1.2-V supply and occupies a core area of 0.82 mm2 including a PLL.

Accurate Transistor Modeling by Three-Parameter Pad Model for Millimeter-Wave CMOS Circuit Design

This paper proposes accurate CMOS device de-embedding and modeling methods. For millimeter-wave circuit design, accurate simulation models are required. For this reason, an accurate measurement is a key technique for device characterization, and de-embedding and modeling methods are also very important. In this work, a three-parameter pad model based on L-2L de-embedding method and a transistor model with frequency and bias dependency are proposed. The pad model is derived from the assumption that the capacitance of PADs becomes constant at high frequencies. In the transistor modeling, parasitic elements are extracted mathematically. A five-stage low-noise amplifier is fabricated by 65-nm CMOS technology to confirm the accuracy of simulation, and the simulation and measurement results match well with each other.

Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS

A 60GHz antenna switching architecture is presented for millimeter-wave transceivers. This circuit topology re-uses the last stage’s transistor of power amplifier (PA) and the first stage’s transistor of low-noise amplifier (LNA) as switches, and the matching blocks. A two-stage LNA and a two-stage PA are designed considering antenna switching operation in 65 nm CMOS. The method has lower loss than conventional switches in receiver mode. The most important advantage is no additional area penalty compared to conventional methods. 2.9 dB minimum noise figure (NF) in the receiver mode is measured, and 2 dBm of OP1dB is measured in the transmitter mode.

A low-loss 60GHz integrated antenna switch in 65nm CMOS

A 60GHz integrated antenna switching architecture is presented for millimeter-wave transceiver system. This circuit topology re-uses the last stages transistor of power amplifier (PA) and the first stages transistor of low-noise amplifier (LNA) as the switching elements, and the matching blocks for PA and LNA. A two-stage LNA and a two-stage PA integrated together as antenna switch is fabricated on 65nm CMOS process. The presented method has lower loss than conventional quarter-wavelength based switches theoretically. LNA and PA are designed considering switching operation; hence there is less area penalty when compared with conventional methods. 2.9dB minimum noise figure (NF) in the receiver mode is measured, and 2 dBm of OP1dB is measured in the transmitter mode.