Korkut Kaan Tokgoz

13.3 A 56Gb/s W-band CMOS wireless transceiver

This paper presents a 56Gb/s 16-QAM 65nm CMOS transceiver using a W-band carrier. Two wideband IF signals are up- and downconverted simultaneously with 68GHz and 102GHz carriers. The transceiver achieves 56Gb/s data-rate with TX-to-RX EVM of -16.5dB within 0.1m distance. The transceiver consumes 260mW and 300mW from a 1V supply in TX and RX modes, respectively. This results in 10pJ/bit efficiency, which is a state-of-the-art-efficient high-data-rate mm-Wave CMOS transceiver.

A Fractional- N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined phase-interpolator and DTC enables efficient design of the multi-phase generation mechanism required for the fractional operation. This technique can be used for designing a fractional-N PLL with low in-band phase noise and low spurious tones with low power consumption. The short-current-free pipelined phase-interpolator used in this work is capable of achieving high-linearity with low-power while minimizing the intrinsic jitter. A number of other circuit techniques and layout techniques are also employed in this design for ensuring high-performance operation with minimal chip area and power consumption. The proposed fractional-N PLL is implemented in standard 65 nm CMOS technology. The PLL has an operating range of 600 MHz from 4.34 GHz to 4.94 GHz. In fractional-N mode, the proposed PLL achieves -249.5 dB FoM and less than -59 dBc fractional spurs.

L-2L de-embedding method with double-T-type PAD model for millimeter-wave amplifier design

For millimeter-wave CMOS circuit design, accurate device models are necessary. Especially an accurate de-embedding method is very important. Hence, precise deembedding of pad parasitics is the first and valuable step to achieve accurate device models. In this work, a new pad modeling based on an L-2L de-embedding is proposed. The pad model is derived with an assumption that characteristic impedance of transmission line becomes constant at high frequency. Every device used in an amplifier is characterized with the proposed de-embedding method, and simulation and measurement results well agree with each other up to 110 GHz.

A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB

This paper presents a fractional-N PLL working in sub-sampling mode using a pipelined phase-interpolator. The proposed pipelined phase-interpolator can achieve high phase linearity with very low power consumption. The fractional-N sub-sampling PLL is implemented in a standard 65nm CMOS technology. The PLL works at a frequency ranging from 4.3GHz to 4.9GHz while consuming 3.3mW. The measured in-band phase noise in fractional-N mode is -114dBc/Hz at 400kHz offset from the carrier, while working with a bandwidth of approximately 2MHz. The combination of high-precision low-power phase-interpolation technique and the sub-sampling technique realizes a high-performance fractional-N frequency synthesizer with the highest reported FoM.

24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance

The 60GHz carrier with 9GHz bandwidth enables ultra-high-speed wireless communication in recent years [1–4]. To meet the demand from rapidly-increasing data traffic, the IEEE802.11ay standard is one of the most promising candidates aiming for 100Gb/s data-rate. Both higher-order digital modulation such as 128QAM and channel bonding at 60GHz are considered to be used in the IEEE802.11ay standard. However, the more severe requirements of LO feedthrough (LOFT) and image-rejection ratio (IMRR) have to be satisfied, so much higher accuracy in built-in calibration circuitry is required across the entire 9GHz spectrum for LOFT and I/Q imbalance calibration to achieve the required EVM.

Accurate Transistor Modeling by Three-Parameter Pad Model for Millimeter-Wave CMOS Circuit Design

This paper proposes accurate CMOS device de-embedding and modeling methods. For millimeter-wave circuit design, accurate simulation models are required. For this reason, an accurate measurement is a key technique for device characterization, and de-embedding and modeling methods are also very important. In this work, a three-parameter pad model based on L-2L de-embedding method and a transistor model with frequency and bias dependency are proposed. The pad model is derived from the assumption that the capacitance of PADs becomes constant at high frequencies. In the transistor modeling, parasitic elements are extracted mathematically. A five-stage low-noise amplifier is fabricated by 65-nm CMOS technology to confirm the accuracy of simulation, and the simulation and measurement results match well with each other.

Cross-line characterization for capacitive cross coupling in differential millimeter-wave CMOS amplifiers

An electrically symmetric cross-line and its characterization are proposed for capacitive cross coupling in differential amplifiers. The characterization of the device is done using two structures. L-2L method is applied to achieve virtual-thru connection of Ground-Signal-Signal- Ground (GSSG) pads and fixtures used in cross-line characterization structures. Pad parasitics are modeled with T-model which provides more accurate results than Π-model. Characterization of cross-line is done using one structure and verified with the other. Comparisons show well aggrement in terms of four-port S-parameter responses up to 67 GHz.

Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS

A 60GHz antenna switching architecture is presented for millimeter-wave transceivers. This circuit topology re-uses the last stage’s transistor of power amplifier (PA) and the first stage’s transistor of low-noise amplifier (LNA) as switches, and the matching blocks. A two-stage LNA and a two-stage PA are designed considering antenna switching operation in 65 nm CMOS. The method has lower loss than conventional switches in receiver mode. The most important advantage is no additional area penalty compared to conventional methods. 2.9 dB minimum noise figure (NF) in the receiver mode is measured, and 2 dBm of OP1dB is measured in the transmitter mode.

A 100–123GHz CMOS frequency doubler with 5.5dBm output power and high fundamental rejection

This paper presents a frequency doubler that operates at W-band and D-band frequencies between 100GHz to 123GHz. An optimized buffering method is proposed to achieve saturated output power as high as 5.5dBm with over 60dBc rejection of the fundamental frequency at −8dBm input power. The overall circuit power consumption is 116mW. The doubler was designed and implemented using 65nm CMOS technology.

Comparison between L-2L and thru-reflect-line de-embedding methods for W-band CMOS amplifier design

L-2L de-embedding method was proved accurate at millimeter-wave (mm-wave) frequencies around 60GHz. However, it was never quantitatively compared to a more complicated method at frequencies as high as 100GHz. In this paper, L-2L and TRL de-embedding methods are compared by applying both on test structures fabricated using CMOS 65nm process. More focus will be given to the W-band frequencies by comparing the measurement results of a W-band amplifier with simulation results that are based on both of the de-embedding methods.