Jun Kudo

High-Temperature Etching of PZT/Pt/TiN Structure by High-Density ECR Plasma

Submicron patterning technologies for the PZT/Pt/Ti/TiN/Ti structure with a spin on glass (SOG) mask were demonstrated using a high-density ECR plasma and a high substrate temperature above 300° C. A 30%-Cl2/Ar gas was used to etch a lead zirconate titanate (PZT) film. No deposits remained, which resulted in an etched profile of more than 80°. A 40%-O2/Cl2 gas was used to etch a Pt film. The etching was completely stopped at the Ti layer. 30-nm-thick deposits remained on the sidewall. They were removed after dipping in hydrochloric acid. The etched profile of a Pt film was more than 80°. The Ti/TiN/Ti layer was etched with pure Cl2 gas. The size shift from the SOG mask was less than 0.1 µ m. Interdiffusion between SOG and PZT was not detected by transmission electron microscopy and energy dispersive X-ray spectroscopy (TEM-EDX) analysis.

A half-micron ferroelectric memory cell technology with stacked capacitor structure

A half-micron ferroelectric technology applicable to mega-bit non-volatile memories is reported. 10.5 /spl mu/m/sup 2/ 1transistor/1capacitor cell with a stacked capacitor structure is successfully achieved using planarization by CMP (chemical mechanical polishing), dry etching at the high temperature and TiO/sub 2/ diffusion barrier technologies. The capacitance above 50 fF is obtained at the size of 1.5 /spl mu/m/spl times/1.5 /spl mu/m, which satisfies the primary requirements for 4M NVDRAM operation.<<ETX>>

Barrier properties for oxygen diffusion in a TaSiN layer

Annealing in O2 at temperatures above 650° C is required for a thin ferroelectric capacitor. Reduction of the leakage current and an increase of capacitance can be attained in the charge storage capacitor through this annealing. A stacked structure capacitor cell must be practically employed in metal oxide semiconductor large scale integrated circuits (MOSLSI). In this capacitor cell with a conventional Pt/TiN/poly-Si lower electrode, however, O2 annealing can not be attained at high temperature because peeling of the TiN barrier layer and the formation of a thin oxide layer at the surface of poly-Si occur. An noncrystalline TaSiN layer has been studied with respect to the barrier effect for oxygen diffusion used in the barrier layer of the lower electrode. The penetration depth of oxygen diffusion decreases markedly with increasing Si composition in a TaSiN layer and reaches 20 nm deep in a Ta.22Si.35N.43 layer. However, the resistivity increases with this increase. A good diffusion barrier layer with low sheet resistance is attained in a Ta.50Si.16N.34 layer. Penetration depth below 40 nm is obtained in a slightly Si-rich Ta.36Si.27N.37 layer for O2 annealing at 850° C.

Barrier Effect of TaSiN Layer for Oxygen Diffusion

The barrier effect for oxygen diffusion is studied in TaSiN layers. The TaSiN is deposited by reactive sputtering employing Ta and Si targets. The composition of the layer ranges from Ta{sub 0.16}Si{sub 0.27}N{sub 0.57} to Ta{sub 0.55}Si{sub 0.07}N{sub 0.38} by varying the Ta target power from 100 to 400 watts (W). A resistivity of 210 {micro}{Omega} cm is obtained for the Ta{sub 0.55}Si{sub 0.07}N{sub 0.38} layer. The surface oxidation and in-diffusion of oxygen to a depth of 15 nm into the Ta{sub 0.30}Si{sub 0.17}N{sub 0.53} layer are observed by annealing in O{sub 2} at 650 C. However, the oxygen diffusion is suppressed in the Ta{sub 0.55}Si{sub 0.07}N{sub 0.38} layer. No out-diffusion of oxygen occurs from the Ta{sub 2}O{sub 5} dielectric layer to the amorphous barrier layer. This result shows that a low Si concentration layer for instance, Ta{sub 0.55}Si{sub 0.07}N{sub 0.38} is a promising barrier layer for oxygen diffusion and is useful for charge storage capacitors for MOS memory devices.

The degradation of ferroelectric properties of PZT thin films due to plasma damage

Abstract The degradation of ferroelectric properties of PZT films due to plasma damage were investigated. Hysteresis loop and leakage current of PZT films were measured before and after plasma exposure and plasma etching. The damage related defects equivalent to positive charge and neutral traps were introduced into PZT films. Recovery of the plasma damage required annealing at 550°C. The influence of deposition damage of SiO2 using TEOS-O3 also was investigated.

MOCVD Growth of InP on 4-inch Si Substrate with GaAs Intermediate Layer

This letter describes the heteroepitaxy of InP on Si by MOCVD. A new epitaxial structure with a thin GaAs intermediate layer (InP/GaAs/Si) is proposed to alleviate the large lattice mismatch (8.4%) between InP and Si. Using this structure, a 4-inch InP single crystal with a mirror-like surface and good thickness uniformity (Δd/d=±10%) was obtained. Residual stress in the InP film was 5.7±108 dyn/ cm2 for the InP/GaAs/Si structure, as compared to 8.3×108 dyn/cm2 for the InP directly grown on Si. This shows that the GaAs intermediate layer is also effective in reducing the residual stress in the InP epilayer.

Epitaxial growth of InP on Si by OMVPE — defect reduction in epitaxial InP using InAsxP1−xInP superlattices

Abstract The heteroepitaxy of InP on Si substrates was investigated using OMVPE. A new epitaxial structure with a GaAs intermediate layer, 100 nm thick, was used to alleviate the 8.4% lattice mismatch between InP and Si. Four-inch size InP single crystal with a specular surface and good thickness uniformity ( Δd d =±8% ) was reproducibly obtained. It was found that the GaAs intermediate layer effectively reduced the residual stress in the InP epilayer and 8.4×10 8 dyn/cm 2 was obtained. The EPD of the as-grown epilayer, etched by HBr+H 3 PO 4 solution, was on the order of 10 8 cm −2 and it decreased to (2−4)×10 7 cm −2 by post growth annealing in PH 3 +PH 2 ambient. To further reduce crystalline defects, a buffer layer consisting of ten periods of InAs x P 1− x (2.5 nm)InP(2.5 nm) was formed between the InP epilayers grown on both as-grown and annealed InP/GaAs/Si substrates ( x =0.3). This superlattice buffer layer reduced the EPD of these epilayers to 30–50%. Using a stacked structure with superlattice buffer layer and annealed InP/GaAs/Si substrate, an InP epitaxial layer with EPD of 1×10 7 cm −2 was obtained.

Fine-Grained SrBi2Ta2O9 Thin Films by Low Temperature Annealing

A new low pressure annealing method for preparation of SrBi2Ta2O9 thin films is proposed. These thin films were prepared on Pt/TiO2/SiO2/Si substrates by the metalorganic decomposition (MOD) method, and their structural and electrical properties were investigated. Low pressure annealing was performed at 650°C for 60 min in a 2 Torr oxygen ambient per coating. The films were well crystallized and exhibited fine-grained and dense structures with grain size of about 50 nm. Pr=4.9 µC/cm2, Ec=24 kV/cm, IL=8.6×10-8 A/cm2 at a applied voltage of 3 V and breakdown voltage (VB) of over 20 V were obtained for the 200-nm-thick films. Futhermore, in the 100-nm-thick SBT film, a saturation voltage of 1 V was obtained. Pr=3.6 µC/cm2, Ec=25 kV/cm, IL=5.5×10-8 A/cm2 at 1 V and VB was over 10 V. Therefore, this method is very useful for highly integrated ferroelectric nonvolatile memory application.

Seeded Electron Beam Recrystallization of Large Area SOI Using Striped Tungsten Encapsulation Technique

Large area SOI (silicon on insulator) film with (001) orientation has been produced by applying a seeded electron beam recrystallization technique to the specimen with striped encapsulation. The encapsulation stripes consisted of tungsten and polysilicon. A pseudoline electron beam was scanned parallel to the stripes. A 400 µm×800 µm area had become a single crystal including subgrain boundaries in one sweep. These subgrain boundaries were confined to the region between the encapsulation stripes. The orientation of the crystal gradually rotates from (001)[110] to (103)[33] as recrystallization propagated away from the seed.

High Temperature Barrier Electrode Technology for High Density Ferroelectric Memories with Stacked Capacitor Structure

This paper describes the novel stacked electrode structure, PtRhO x /PtRh/PtRhO x , applicable to stacked memory cells in advanced ferroelectric memories. This structure acts as a stable bottom electrode and a barrier on a polysilicon plug up to 700°C and a stable contact resistance of 1.5 KΩ is obtained at the contact size of 0.6 μm. In addition to the low leakage current of lead zirconate titanate [PZT, Pb(Zr 0.52 Ti 0.48 )O 3 ] capacitor (10 8 A/cm 2 at 3 V), degradation properties of fatigue and imprint are improved compared with conventional Pt electrodes. The decrease of the switched charge is restricted to less than 10% after the fatigue cycle of 10 11 . These results indicate its promise as a barrier electrode structure for advanced ferroelectric memory integration.