Sen-Wen Hsiao

Periodic jitter and bounded uncorrelated jitter decomposition using incoherent undersampling

Jitter measurement is an essential part for testing high speed digital I/O and clock distribution networks. Precise jitter characterization of signals at critical internal nodes provides valuable information for hardware fault diagnosis and next generation design. Recently, incoherent undersampling has been proposed as a low-cost solution for signal integrity characterization at high data rate. Incoherent undersampling drastically reduces the sampling rate compared to Nyquist rate sampling without relying on the availability of a data synchronous clock. In this paper, we propose a jitter decomposition and characterization method based on incoherent undersampling. Associated fundamental period estimation techniques along with properties of incoherent undersampling, are used to isolate the effects of periodic and periodic crosstalk jitter. Mathematical analysis and hardware experiments using commercial off-the-shelf components are performed to prove the viability of the proposed method.

A programmable BIST design for PLL static phase offset estimation and clock duty cycle detection

Reference spur is a nonlinear effect and important specification in PLL for long term jitter. Periodic events of reference clock create a static phase offset between signals. The finite phase offset comes from charge pump mismatch and layout asymmetry. This paper presents a built-in self-test (BIST) circuit applied for PLL static phase offset (SPO) estimation. The proposed circuit takes advantage of an integrator for time-to-voltage conversion (TVC). Along with comparators and counters, a BIST can be constructed for an estimation of mismatch ratio down to 1% over process corners in simulation (10 psec for lnsec pulse width). The calibration can be operated in a closed-loop PLL with lock signal. Additional circuits including delay lines and non-inverting amplifiers are designed for fast calibration. The result shows at least 27 times faster detection speed can be achieved over process corners. The phase offset between PLL reference and feedback signal is essentially the duty cycle difference, and the test is also applied for duty cycle distortion. Related analysis and measurement are included.

Incoherent Undersampling-Based Waveform Reconstruction Using a Time-Domain Zero-Crossing Metric

Incoherent undersampling-based waveform acquisition provides a low-cost test setup for characterizing high-speed systems. A periodic waveform reconstruction using incoherent undersampling remaps time indices of samples using the modulus of the suspected period of the signal, effectively folding the signal into a time window equal to one period. The major cost and accuracy limitations of the reconstruction technique arise from estimation of the waveform period. Multiple cost functions have been proposed to estimate the period, including frequency domain metrics, which are computationally intensive. In this paper, we propose a new time domain zero-crossing (ZC)-based metric, where the metric gives the number of ZC in the reconstructed waveform for an assumed period of the waveform. The reconstruction technique is also extended to beyond the track-and-hold amplifier bandwidth using a novel test setup combining the incoherent undersampling with multichannel bandwidth interleaving.

Low Cost Built-in Sensor Testing of Phase-Locked Loop Dynamic Parameters

Phase-locked loops (PLLs) serve as core building blocks for communication systems and are often used to synthesize IO clocks for data synchronization and frequency sources for RF conversion. Testing of PLL loop performance is consequently important for guaranteeing the reliability of the underlying communication systems. In this paper, a low cost testing method based on loop triggering and use of built-in analog sensors (small number of transistors) to accurately predict phase-locked loop dynamic parameters is proposed. The sensor responses show strong statistical correlation with the PLL parameters being tested. Accordingly, supervised learning is applied to predict the required PLL parameters from the observed sensor response after “training”. In order to verify analog sensor testing in PLL loop response evaluation, an off-the-shelf PLL and a PLL on printed circuit board (PCB) are tested using this method. The results are analyzed and shown with high correlation to loop parameters. Parameters including charge pump current, voltage-controlled oscillator (VCO) gain, bandwidth, phase margin, and locking time are predicted accurately to prove the viability of the proposed test method.

Time Domain Reconstruction of Incoherently Undersampled Periodic Waveforms Using Bandwidth Interleaving

Incoherent undersampling provides a low cost solution for wideband periodic waveform acquisition without the requirement for synchronization with the source clock. The bandwidth of a traditional incoherent undersampling based test setup is limited by the the bandwidth of the track and hold amplifier. In this work, a test setup is proposed combining incoherent undersampling and bandwidth interleaving to break the bandwidth barrier of the track and hold amplifier. The high frequency components of the signal waveform beyond the track and hold bandwidth are down converted using mixers and undersampled. While bandwidth interleaved frequency domain signal reconstruction techniques have been proposed before, this is the first time that fast time domain reconstruction techniques are used for periodic waveform reconstruction of wideband signals in the absence of any synchronization between the test signal and the tester oscillator/sampling clock over multiple frequency bands by choosing the local oscillator frequency to be a multiple of the sampling frequency. The periodic test signal waveform is acquired over multiple channels each covering only part of the total bandwidth of the signal. Feasibility of the proposed technique is shown through simulation and hardware results.

Concurrent Multi-Channel Crosstalk Jitter Characterization Using Coprime Period Channel Stimulus

In recent years, the use of highly parallelized and high-speed data links has exacerbated the problem of crosstalk coupling. Signals with high frequency components couple to and degrade the quality of signals in adjacent lines aggressively with reduced device dimensions. In this paper, we propose a methodology for characterizing multiple crosstalk jitter effects in the time domain using a single data capture without the use of any channel models. The method uses repetitive data patterns across different signal lines with coprime periods. Each signal with crosstalk effects is digitized using sub-Nyquist sampling, and after back-end digital signal processing, the original transmitted signal on each line is isolated from its crosstalk components. Mathematical analysis shows that only by using patterns with coprime lengths, unbiased crosstalk characterization is possible. Hardware measurements support the proposed test methodology.

Phase-locked loop design with SPO detection and charge pump trimming for reference spur suppression

As an important factor for long-term jitter in clock synthesis and distribution, reference spurs result from circuit mismatch and nonlinear effects that induce periodic perturbations in phase-locked loops (PLLs). In this paper, a PLL with built-in static phase offset (SPO) detector and charge pump current trimming for self-calibration circuits is proposed. By adjusting the charge pump current ratio determined by an SPO detector, minimum and maximum improvements of 12dB and 22.99dB in reference spur suppression can be achieved. The best improvement reduces the integrated jitter by 10% over a 10kHz to 10MHz bandwidth. The technique is demonstrated for a PLL output frequency from 400 MHz to 1 GHz. The ring oscillator based PLL is designed with 200 KHz bandwidth and 70 degree phase margin. Measurement results from chips across different corners are provided to verify the calibration technique.

24GHZ dual core PLL design for 60 GHz transceiver and efficient validation methodology

Design and validation of millimeter-wave (MMW) devices is a significant challenge due to the design difficulties in meeting GHz performance constraints and the cost and complexity of test instrumentation needed to validate the circuits. In this paper a 1-V dual-core 24GHz PLL design is presented and it is shown how relatively low cost test instruments utilizing incoherent undersampling can be used to verify the noise performance of a PLL. The 24GHz PLL is implemented to provide more frequency margin and reliability for a 60GHz super-heterodyne transceiver. The incoherent undersampling method is proposed to test different performances of the PLL. Measurement results applying a sampling frequency below 1 GHz are shown for frequency reconstruction and jitter separation.

A PROGRAMMABLE 1-V CMOS 65 nm FREQUENCY SYNTHESIZER DESIGN IN 60 GHz WIRELESS TRANSCEIVER

The paper proposes a CMOS 65 nm 24 GHz wide-band frequency synthesizer with programmability on acquisition speed and supply voltage for low power application in 60 GHz millimeter-wave (mmW) wireless transceiver. The role of mmW phase-locked loop (PLL) is significant for supporting 7 GHz bandwidth across the four channels in IEEE 802.15.3c. The PLL is introduced with consideration of system specifications, as well as the design of individual block. In order to maintain the dynamic behavior of a PLL, two control parameters of its loop transfer function are used for programmability, including the charge pump current and pole-zero position. A regulator is also adopted for supply noise suppression. The Voltage-Controlled Oscillator (VCO) covers frequency range from 24.2 to 29.3 GHz, with 19.1% tuning range. On top of the oscillator, a 1.2 V LDO (Low-Dropout Regulator) with 0.2 V dropout voltage is introduced to increase the immunity against low frequency noise fluctuation from supply. With the proposed structure, the PLL provides a loop bandwidth from 0.94 to 2.05 MHz. The phase margin is larger than 54° and the locking time can be adjusted 16% faster than nominal case. The VCO has better power supply rejection ratio (PSRR) of -48 dB, and Phase Noise of -94 dBc/Hz at 1 MHz frequency offset of 24 GHz.