Nicholas Tzou
Georgia Institute of Technology
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Publication
Featured researches published by Nicholas Tzou.
international test conference | 2012
Nicholas Tzou; Debesh Bhatta; Sen-Wen Hsiao; Hyun Woo Choi; Abhijit Chatterjee
Acquisition of wide bandwidth signals is a significant problem in manufacturing test due to the cost of test equipment driven by the use of high-speed sample and hold circuitry and difficulty in data-clock synchronization. We propose to combine frequency interleaved down conversion (to overcome the bandwidth limitations of sample and hold circuitry) with incoherent undersampling (to overcome data-clock synchronization and ADC speed issues) to design a low cost instrumentation for high speed signal capture. A novel signal reconstruction algorithm is developed along with a method for calibrating the effects of unknown delays in data acquisition hardware due to mismatch in signal path lengths on the reconstructed signal. Simulation results and preliminary hardware validation prove the feasibility of the proposed technique.
design, automation, and test in europe | 2013
Nicholas Tzou; Debesh Bhatta; Sen-Wen Hsiao; Abhijit Chatterjee
Jitter measurement is an essential part for testing high speed digital I/O and clock distribution networks. Precise jitter characterization of signals at critical internal nodes provides valuable information for hardware fault diagnosis and next generation design. Recently, incoherent undersampling has been proposed as a low-cost solution for signal integrity characterization at high data rate. Incoherent undersampling drastically reduces the sampling rate compared to Nyquist rate sampling without relying on the availability of a data synchronous clock. In this paper, we propose a jitter decomposition and characterization method based on incoherent undersampling. Associated fundamental period estimation techniques along with properties of incoherent undersampling, are used to isolate the effects of periodic and periodic crosstalk jitter. Mathematical analysis and hardware experiments using commercial off-the-shelf components are performed to prove the viability of the proposed method.
IEEE Transactions on Signal Processing | 2015
Thomas Moon; Hyun Woo Choi; Nicholas Tzou; Abhijit Chatterjee
A new undersampling-based dual-rate signal acquisition technique for measuring a wideband sparse signal (i.e., a multiband signal) is presented in this paper. The proposed architecture employs a combination of dual-rate time-interleaved undersampling hardware and associated multicoset back-end signal processing algorithms. In dual-rate sampling hardware, a pair of uniform samplers is used to acquire a common incoming wideband sparse signal while the operation frequencies of the two samplers have a small frequency offset. Due to the sampling frequency offset, the time grids of the samples obtained from the two samplers are irregularly spaced. These nonuniform periodic samples are then digitally re-sequenced and applied as input to a multicoset signal reconstruction algorithm. The multicoset signal reconstruction algorithm uses the re-sequenced nonuniform periodic samples to achieve a perfect reconstruction of the original wideband signal with an enhanced time resolution beyond the sampling hardwares capability. Compared to the conventional multi-channel sampling approach commonly used with multicoset algorithms, the proposed method uses fewer sampling channels and does not require their accurate clock phase adjustment.
vlsi test symposium | 2013
Sen-Wen Hsiao; Nicholas Tzou; Abhijit Chatterjee
Reference spur is a nonlinear effect and important specification in PLL for long term jitter. Periodic events of reference clock create a static phase offset between signals. The finite phase offset comes from charge pump mismatch and layout asymmetry. This paper presents a built-in self-test (BIST) circuit applied for PLL static phase offset (SPO) estimation. The proposed circuit takes advantage of an integrator for time-to-voltage conversion (TVC). Along with comparators and counters, a BIST can be constructed for an estimation of mismatch ratio down to 1% over process corners in simulation (10 psec for lnsec pulse width). The calibration can be operated in a closed-loop PLL with lock signal. Additional circuits including delay lines and non-inverting amplifiers are designed for fast calibration. The result shows at least 27 times faster detection speed can be achieved over process corners. The phase offset between PLL reference and feedback signal is essentially the duty cycle difference, and the test is also applied for duty cycle distortion. Related analysis and measurement are included.
vlsi test symposium | 2012
Thomas Moon; Nicholas Tzou; Xian Wang; Hyun Woo Choi; Abhijit Chatterjee
In this paper, we propose a wideband signal reconstruction scheme for testing high-speed pseudo random bit sequences (PRBSs) in the presence of jitter noise using incoherent sampling. The proposed approach exploits synchronous multirate sampling (SMRS) hardware and multicoset back-end signal processing algorithms. The SMRS hardware consists of multiple analog-to-digital converters (ADCs) whose sampling frequencies are synchronized with a common frequency reference and can be individually configured. The optimal sampling frequency of each ADC is chosen based on the input signal information and sampling hardware specifications. As compared to other sampling hardware used for multicoset signal reconstruction, the proposed approach uses less number of ADCs and does not require accurate sampling clock phase adjustment. In the digital signal reconstruction, the input waveform is reconstructed by the multicoset signal processing algorithms and the phase noise of each tone of the PRBS test signal is measured.
Journal of Electronic Testing | 2015
Nicholas Tzou; Debesh Bhatta; Barry John Muldrey; Thomas Moon; Xian Wang; Hyun Woo Choi; Abhijit Chatterjee
Characterizing the spectrum of sparse wideband signals of high-speed devices efficiently and precisely is critical in high-speed test instrumentation design. Recently proposed sub-Nyquist rate sampling systems have the potential to significantly reduce the cost and complexity of sparse spectrum characterization; however, due to imperfections and variations in hardware design, numerous implementation and calibration issues have risen and need to be solved for robust and stable signal acquisition. In this paper, we propose a low-cost and low-complexity hardware architecture and associated asynchronous multi-rate sub-Nyquist rate sampling based algorithms for sparse spectrum characterization. The proposed scheme can be implemented with a single ADC or with multiple ADCs as in multi-channel or band-interleaved sensing architectures. Compared to other sub-Nyquist rate sampling methods, the proposed hardware scheme can achieve wideband sparse spectrum characterization with minimum cost and calibration effort. A hardware prototype built using off-the-shelf components is used to demonstrate the feasibility of the proposed approach.
international test conference | 2012
Xian Wang; Hyun Woo Choi; Thomas Moon; Nicholas Tzou; Abhijit Chatterjee
In this paper, a higher than Nyquist RF test waveform synthesizer with digital phase noise injection is proposed. The proposed system uses time-interleaved digital-to-analog converters (DACs) and associated digital signal processing algorithms to enhance the spectral image of the synthesized waveform in the high-order Nyquist zones by increasing the effective sampling rate and eliminating unwanted signals inside the bandwidth of interest. The generated spectral images are used as the primary output of the proposed system. The waveform synthesizer is capable of digitally controlling the phase noise characteristics of the output signal in the high-order Nyquist zones. In addition, it utilizes relatively low-cost off-the-shelf integrated circuits (ICs) for multi-GHz signal generation. In hardware validation, dual DACs operating at 2.5Gb/s (effective Nyquist rate of 5 Gb/s) are used to generate a signal centered at 3.2GHz (corresponding to a Nyquist rate of 6.4 GHz). In addition, controlled phase noise generation is demonstrated.
IEEE Transactions on Very Large Scale Integration Systems | 2015
Debesh Bhatta; Nicholas Tzou; Joshua W. Wells; Sen-Wen Hsiao; Abhijit Chatterjee
Incoherent undersampling-based waveform acquisition provides a low-cost test setup for characterizing high-speed systems. A periodic waveform reconstruction using incoherent undersampling remaps time indices of samples using the modulus of the suspected period of the signal, effectively folding the signal into a time window equal to one period. The major cost and accuracy limitations of the reconstruction technique arise from estimation of the waveform period. Multiple cost functions have been proposed to estimate the period, including frequency domain metrics, which are computationally intensive. In this paper, we propose a new time domain zero-crossing (ZC)-based metric, where the metric gives the number of ZC in the reconstructed waveform for an assumed period of the waveform. The reconstruction technique is also extended to beyond the track-and-hold amplifier bandwidth using a novel test setup combining the incoherent undersampling with multichannel bandwidth interleaving.
asian test symposium | 2013
Debesh Bhatta; Nicholas Tzou; Sen-Wen Hsiao; Abhijit Chatterjee
Incoherent undersampling provides a low cost solution for wideband periodic waveform acquisition without the requirement for synchronization with the source clock. The bandwidth of a traditional incoherent undersampling based test setup is limited by the the bandwidth of the track and hold amplifier. In this work, a test setup is proposed combining incoherent undersampling and bandwidth interleaving to break the bandwidth barrier of the track and hold amplifier. The high frequency components of the signal waveform beyond the track and hold bandwidth are down converted using mixers and undersampled. While bandwidth interleaved frequency domain signal reconstruction techniques have been proposed before, this is the first time that fast time domain reconstruction techniques are used for periodic waveform reconstruction of wideband signals in the absence of any synchronization between the test signal and the tester oscillator/sampling clock over multiple frequency bands by choosing the local oscillator frequency to be a multiple of the sampling frequency. The periodic test signal waveform is acquired over multiple channels each covering only part of the total bandwidth of the signal. Feasibility of the proposed technique is shown through simulation and hardware results.
vlsi test symposium | 2012
Nicholas Tzou; Thomas Moon; Xian Wang; Hyun Woo Choi; Abhijit Chatterjee
In this paper, we propose a new test response acquisition technique for high-speed devices-based on dual-frequency incoherent sub-sampling and sparse signal reconstruction. The proposed technique enables reconstruction of spectrally sparse wideband signals such as multi-tone signals and short pseudo-random bit sequences (PRBS) with enhanced time/frequency resolution as opposed to current methods. The sampling hardware utilizes dual analog-to-digital converters (ADCs) and dedicated sampling frequency synthesizers with a common frequency reference. As compared to other compressive sampling architectures [1], the proposed hardware architecture is easy to implement at low cost since it does not require accurate sampling clock phase adjustment or random timing generation. For digital signal reconstruction, the proposed technique requires less number of waveform samples than conventional equivalent-time sampling techniques. In addition, the use of an resolution-enhanced discrete Fourier transform (DFT) frame and basis pursuit algorithms minimizes spectral leakage of incoherently sub-sampled signals. This co-design of sampling hardware and signal reconstruction algorithms enables testing of spectrally sparse wideband signals with enhanced time/frequency resolution.