Hyun Woo Choi

Signal Acquisition of High-Speed Periodic Signals Using Incoherent Sub-Sampling and Back-End Signal Reconstruction Algorithms

This paper presents a high-speed periodic signal acquisition technique using incoherent sub-sampling and back-end signal reconstruction algorithms. The signal reconstruction algorithms employ a frequency domain analysis for frequency estimation, and suppression of jitter-induced sampling noise. By switching the sampling rate of a digitizer, the analog frequency value of the sampled signal can be recovered. The proposed signal reconstruction uses incoherent sub-sampling to reduce hardware complexity. The results of simulation and hardware experiments indicate that the proposed signal reconstruction algorithms are able to reconstruct multi-tone high-speed periodic signals in the discrete time domain. The new signal acquisition technique simplifies signal acquisition hardware for testing and characterization of high-speed analog and digital signals.

Iterative built-in testing and tuning of mixed-signal/RF systems

Design and test of high-speed mixed-signal/RF circuits and systems is undergoing a transformation due to the effects of process variations stemming from the use of scaled CMOS technologies that result in significant yield loss. To this effect, postmanufacture tuning for yield recovery is now a necessity for many high-speed electronic circuits and systems and is typically driven by iterative test-and-tune procedures. Such procedures create new challenges for manufacturing test and built-in self-test of advanced mixed-signal/RF systems. In this paper, key test challenges are discussed and promising solutions are presented in the hope that it will be possible to design, manufacture and test “truly self-healing” systems in the near future.

Digitally Assisted Concurrent Built-In Tuning of RF Systems Using Hamming Distance Proportional Signatures

In this paper, a novel built-in tuning technique to compensate for variability induced imperfections in RF subsystems is proposed. The test stimulus is obtained from a filtered digital pattern and the RF response is down-converted using an envelope detector. The resulting signal is mapped to a digital signature, such that the Hamming Distance between the observed and the golden signature represents the degree by which the circuit specifications (Gain, IIP3, EVM, etc) differ from the ideal. A hardware driven algorithm is used to minimize this Hamming Distance to concurrently optimize (tune) multiple RF specifications. As opposed to prior research, the method does not require the use of an on-chip digital signal processor and uses minimal on-chip hardware. Results obtained on a 2.4 GHz transmitter subsystem show significant impact of tuning on device specifications.

Low-cost wideband periodic signal reconstruction using incoherent undersampling and back-end cost optimization

Acquisition of wide bandwidth signals is a significant problem in manufacturing test due to the cost of test equipment driven by the use of high-speed sample and hold circuitry and difficulty in data-clock synchronization. We propose to combine frequency interleaved down conversion (to overcome the bandwidth limitations of sample and hold circuitry) with incoherent undersampling (to overcome data-clock synchronization and ADC speed issues) to design a low cost instrumentation for high speed signal capture. A novel signal reconstruction algorithm is developed along with a method for calibrating the effects of unknown delays in data acquisition hardware due to mismatch in signal path lengths on the reconstructed signal. Simulation results and preliminary hardware validation prove the feasibility of the proposed technique.

EVM Testing of Wireless OFDM Transceivers Using Intelligent Back-End Digital Signal Processing Algorithms

In production testing of wireless systems, measurement of EVM (a critical spec that is directly related to bit error rate) incurs significant test time due to the large numbers of symbols that need to be transmitted for reasons of accuracy. In our approach, EVM is modeled as a function of the system static non-idealities (IQ mismatch, gain, IIP3 parameters) and dynamic non-idealities (system noise, VCO phase noise). Using a selected subset of the OFDM tones, the static parameters are calculated first. These are then used to facilitate noise estimation using a back-end constellation compensation and noise amplification procedure. The data generated is used to predict EVM using machine learning methods. Significant reduction in test time is achieved with little loss in test accuracy.

Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements

A low-cost linearity test methodology for high-resolution analog-to-digital converters (ADCs) is presented in this paper. Linearity testing of ADCs requires high-precision digital-to-analog conversion (DAC) capability, commonly 3-bit higher resolution than the ADC under test. Further, a large number of ADC output data samples must be collected making conventional histogram testing impractical for high-resolution ADCs with 18-24 bit precision. In the proposed test methodology, two low-precision and low-cost DACs are used to generate a high-resolution ADC test stimulus. Significant reductions in test cost and test time are achieved by using low-cost instrumentation and by making fewer measurements than required for conventional histogram test. A least-squares-based polynomial fitting approach is used to determine the transfer function of the ADC under test. The generated transfer function is used to compute the non-linearity of the ADC accurately. No assumption is made regarding the linearity of the lower precision signal generators (DACs) used in the testing procedure. Software simulations and hardware experiments are performed to validate the proposed test methodology.

Jitter Characterization of Pseudo-random Bit Sequences Using Incoherent Sub-sampling

In this paper, jitter analysis algorithms for characterizing timing jitter of multi-Gbps pseudo-random bit sequences (PRBSs) are presented. For signal acquisition, incoherent sub-sampling is employed to increase the effective sampling rate of a digitizer and to simplify its signal acquisition architecture by removing the need for timing synchronization circuits. As a substitute for these circuits, algorithms for signal clock recovery (CR) and waveform reconstruction from the acquired data are developed in this research. The algorithms utilize peak identification of the sampled signal spectrum and the sparsity of the reconstructed waveform in the frequency domain as decision making criteria for accurate signal reconstruction. The jitter value of such a reconstructed waveform is quantified with the use of a wavelet based denoising method to generate a self-reference signal against which zero-crossing times are compared to generate jitter statistics. In addition, the data dependent jitter components can be differentiated from the original jitter by analyzing zero-crossing discrepancies of the self-reference signal.

Enhanced Resolution Jitter Testing Using Jitter Expansion

This paper presents a hardware jitter expansion technique to enable high-resolution jitter measurement of multi-GHz digital signals. To realize high-resolution timing analysis, the jitter is reconstructed on a low-speed signal and jitter measurements are made on this signal instead of the original high-speed signal. The reconstructed jitter on the low-speed signal occurs on a proportionately larger time-scale as opposed to the original jitter on the high-speed signal. Consequently, the jitter on the low-speed signal can be measured easily using conventional jitter measurement techniques and mapped back to its corresponding value relative to the high-speed signal. The approach allows one or two orders of magnitude smaller jitter values to be measured than standard jitter measurement techniques available today. The proposed hardware is easily implemented as a front-end to any existing jitter measurement system. Simulation data and hardware measurements are presented to prove the viability of the proposed scheme.

Low Cost Sparse Multiband Signal Characterization Using Asynchronous Multi-Rate Sampling: Algorithms and Hardware

Characterizing the spectrum of sparse wideband signals of high-speed devices efficiently and precisely is critical in high-speed test instrumentation design. Recently proposed sub-Nyquist rate sampling systems have the potential to significantly reduce the cost and complexity of sparse spectrum characterization; however, due to imperfections and variations in hardware design, numerous implementation and calibration issues have risen and need to be solved for robust and stable signal acquisition. In this paper, we propose a low-cost and low-complexity hardware architecture and associated asynchronous multi-rate sub-Nyquist rate sampling based algorithms for sparse spectrum characterization. The proposed scheme can be implemented with a single ADC or with multiple ADCs as in multi-channel or band-interleaved sensing architectures. Compared to other sub-Nyquist rate sampling methods, the proposed hardware scheme can achieve wideband sparse spectrum characterization with minimum cost and calibration effort. A hardware prototype built using off-the-shelf components is used to demonstrate the feasibility of the proposed approach.

Low cost high-speed test data acquisition: Accurate period estimation driven signal reconstruction using incoherent subsampling

In this paper, we propose a new algorithm to estimate the fundamental period (frequency) of a highspeed pseudo random bit sequence (PRBS) or multitone signal using incoherent subsampling. While incoherent subsampling suffers from spectral leakage due to the mismatch between the input test signal and the discrete Fourier transform (DFT) basis, the proposed algorithm efficiently resolves the spectral leakage problem using a back-end signal process. The approach requires incoherent digitization of the periodic sequence using at least two clocks running at different speeds. No additional hardware to synchronize the input signal frequency with the sampling clock frequency is needed. A new discrete frequency shifting approach for determining the period of the input signal is proposed that is computationally efficient. The signal reconstruction approach has been tested with experimental results.