Seok-Man Kim

Low-Power Touch-Sensing Circuit With Reduced Scanning Algorithm for Touch Screen Panels on Mobile Devices

Touch screen panel (TSP) technology has dramatically enhanced the connectivity between man and machine, in particular within mobile consumer electronics where mobility is a key design criterion. This paper introduces a novel charge-sensing technique derived from the behavioral characteristics of a mutual capacitive touch screen panel. The approach is based on a reduced scan algorithm whereby both the target and its surroundings form the node and the selection process is conducted in two phases. In the first phase, the introduction of a charge on the TSP is sensed, while the second phase evaluates when the touch event occurs on the TSP. The proposed algorithm reduces the number of sensing nodes activated during the waiting period by observing the behavior of a single row within the charge sensing array, as opposed to the more conventional approach in which all TSP nodes are scanned. As a result, power consumption is reduced by 60% during the sensing phase, while the dynamic sensing range is increased by a factor of 38% for a complete two-stage sensing cycle.

Design of a wave-pipelined serializer-deserializer with an asynchronous protocol for high speed interfaces

In this paper, we proposed an asynchronous wave-pipelined Serializer and Deserializer, or WP-SERDES in brief, that is totally clock-free. In contrast to conventional SERDES that employ power hungry phase-locked loops (PLLs) for synchronization in serializers and clock-data recovery (CDR) circuits in deserializers, the proposed WP-SERDES employs delay elements (DEs) consisting of inverter chains for timing reference. Besides, throughput of the proposed WP-SERDES is adjustable thanks to the voltage-controlled inverters used in the DEs. The proposed WP-SERDES which was simulated using 180nm CMOS process shows a 3.9 Gb/s throughput and 2.44 mW power consumption.

Implementation of IEEE 802.11a Wireless LAN

This paper presents an implementation of IEEE802.11a wireless LAN system including a baseband processor and MAC (medium access control). We introduce some innovative techniques improving the performance as well as to fulfill the mandatory requirement of the standard. The evaluation system consists of a test-board with the fabricated base band processor chip and an ARM-base SoC platform for implementing MAC. The baseband processor was fabricated using MagnaChip 0.25 mum CMOS technology, occupying size of 5 mm times 5 mm. The demonstration of WLAN system was successfully donewith various wireless environments AWGN, multi-path Rayleigh fading and Rician one.

Display signal interface techniques for mobile applications

This paper provides an overview of existing interface technologies and current technical trends for mobile applications. In recent times the display signal interface techniques have rapidly improved providing the desired high-resolution and large-size characteristics. Some of design methodologies for enhancement include working with the signal swing of a display interface whereby as it is decreased the data rate is increased accordingly. For flat panel display (FPD) three interface schemes namely, intermodule interface, intra-panel interface and mobile interface have been important as part of the design space and existed according to the physical location of interface system.

A hybrid control scheme for driving current sources of pm-oled panel

This paper proposes a new amplitude width modulation (AWM) scheme for PM-OLED (passive matrix organic light emission device) data driver IC. The data driver controls brightness of OLED by adjusting the amplitude and width of the current through OLED. There are two conventional modulation schemes; pulse amplitude modulation (PAM) and pulse width modulation (PWM). The PWM suffers from lower light emitting efficiency at lower luminance levels. The PAM gives us large chip area, due to DACs for each column. The proposed AWM accurately controls the current level using MSB data and increases luminance using LSB data that improves inefficiencies of the PAM and PWM. We fabricated a one channel data driver chip with AWM using a 0.18 um standard CMOS process. The proposed scheme reduces power consumption 50% compared with PWM.

Touched image transmission of a high resolution touch panel using MIPI CSI-2 for kiosk applications

This paper presents high speed image data transmission using MIPI(mobile industry processor interface) CSI-2(camera serial interface) interface for high resolution touch panels. On MIPI CSI-2, the receiver corrects 1bit error on the header of packets, but just checks errors on the data of packets without correction. If there are errors, the receiver notices these errors to upper layer including application layer. Error-handling is a duty of application layers that will bring touch response delay consequently. In this work, we added an error handling path to low level protocol layer. In addition, to compensate signal attenuation due to increasing transmission distance, the adaptive equalizer using FVC(frequency-voltage converter) was applied to the receiver. The proposed architecture was tuned with 800Mbps that transfers data of 800×600 high resolution panels less than 10ms with a single data lane.

Two-stage charge sensing circuit for a mutual-capacitive touch screen panel

In this paper, we introduce a new charge sensing circuit for a mutual-capacitive touch screen panel (TSP). The circuit senses charges in two stages: a sensing stage and an evaluation stage when the TSP is touched or untouched. This method establishes easier recognition of a touch event on the TSP and reduces the size of the on-chip sensing capacitors. The dynamic sensing range of this TSP is improved by 38% over that of a conventional TSP.

Design of a Clock and Data Recovery Circuit Using the Multi-point Phase Detector

The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period`s multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

Design of an Asynchronous Instruction Cache based on a Mixed Delay Model

Recently, to achieve high performance of the processor, the cache is splits physically into two parts, one for instruction and one for data. This paper proposes an architecture of asynchronous instruction cache based on mixed-delay model that are DI(delay-insensitive) model for cache hit and Bundled delay model for cache miss. We synthesized the instruction cache at gate-level and constructed a test platform with 32-bit embedded processor EISC to evaluate performance. The cache communicates with the main memory and CPU using 4-phase hand-shake protocol. It has a 8-KB, 4-way set associative memory that employs Pseudo-LRU replacement algorithm. As the results, the designed cache shows 99% cache hit ratio and reduced latency to 68% tested on the platform with MI bench mark programs.

Low Power Design of a MIPI Digital D-PHY for the Mobile Signal Interface

In this paper, we design digital D-PHY link chip controling DSI (Display Serial Interface) that meets MIPI (Mobile Industry Processor Interface) standard. The D-PHY supports a high-speed (HS) mode for fast data traffic and a low-power (LP) mode for control transactions. For low power consumption, the unit blocks in digital D-PHY are optionally switched using the clock gating technique. The proposed low power digital D-PHY is simulated and compared with conven tional one about power consumption on each transaction mode. As a result, power consumptions of TX, RX, and total in HS mode decrease 74%, 31%, and 50%, respectively. In LP mode, power reduction rates of TX, RX, and total are 79%, 40%, and 51.5%, separately. We implemented the low power MIPI D-PHY digital chip using CMOS process under 1.2V supply.