Seong-Dong Kim

A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks

A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer with on-chip voltage-controlled oscillator. The chip fully complies with the IEEE 802.15.4 wireless personal area network in sub-gigahertz mode. The cascaded noise figure of the overall receiver is 9.5 dB and the overall transmitter achieves less than 6.3% error vector magnitude for 40 kb/s mode. The chip uses 1.8-V power supply and the power consumption is 25 mW for reception mode and 29 mW for transmission mode

A CMOS continuous-time Gm-C filter and programmable gain amplifier for WPAN receivers

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve low current consumption. High linearity and constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The POA has a voltage gain varying from 0 to 65 dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2 mW from a 1.8 V power supply and occupy an area of 0.19 mm2.

A Fully CMOS Integrated RF Transceiver for Ubiquitous Networks in Sub-GHz ISM-band

A fully CMOS integrated radio frequency (RF) transceiver for wireless sensor networks in sub-GHz ISM-band applications is implemented and measured. The IC is fabricated in 0.18-mum CMOS technology and packaged in LPCC package. The fully monolithic transceiver consists of a receiver, a transmitter and a RF synthesizer with on-chip VCO. The chip fully complies with the IEEE 802.15.4 WPAN standard in sub-GHz mode. The receiver sensitivity is -98 dBm and the transmitter achieves less than 6.3% error vector magnitude (EVM) for 40 kbps mode. The chip uses 1.8 V power supply and the current consumption is 14 mA for reception mode ad 16 mA for transmission mode

Network Bridge System for Interoperation of ZigBee-UPnP Network

Universal Plug and Play (UPnP) is one of the most promising home network middleware technologies because of its straightforward implementation and zero configuration characteristics. However, it has a limitation of the operations only IP based network and proceeding in a single IP subnet. In this paper, we proposed network bridge architecture for UPnP network to interoperate heterogeneous network, UPnP and ZigBee. The proposed network bridge architecture is capable of configuration ZigBee device as a virtual UPnP device. This technique is promising for seamless inter-networking with ZigBee and UPnP network. Also, the architecture of the proposed network bridge architecture can be applied for a future smart home.

Seamless Network Bridge for Supporting Interoperability UPnP-ZigBee

Universal Plug and Play (UPnP) can be applied many home appliances because of its straightforward implementation and zero configuration characteristics. However, it has limitation of the cost and spatial because it has to be used in IP based network. The proposed network bridge is capable of generating virtual Zigbee device without implementing each actual device which inserts an UPnP stack. This technique is promising for seamless inter-networking with Zigbee and UPnP network. Also, the architecture of the proposed network bridgecan be applied implementation for a future smart home.

Design and Implementation of AISG Modem for Antenna Line Device

In this paper, we propose a digital implementation of the antenna interface standards group (AISG) modem for the remote control and monitoring of antenna line devices (ALDs) through an antenna feeder cable. The proposed modem is implemented in Altera EP3C16E144C8 device, together with an 8-bit ADC and a BPF. It operates at variable data rates of 9.6, 38.4, and 115.2 kbps based on the OOK modulation scheme. The carrier frequency of the OOK modulated signals is 2.176 MHz. The modem is fully compliant with the 3GPP and AISG standards. To show the validity of the proposed AISG modem, the modem is implemented in FPGA and its functionality is verified using the verification scenario of 3GPP and AISG standards. The proposed AISG modem consumes 0.41 W and 0.6 W with DC power supplies of 10 V and 32 V, respectively. The measured transmit power level is +3.3 dBm, and the measured return loss in pass-band is more than 10 dB. The duty cycle variations for data rates of 9.6, 38.4, and 115.2 kbps are less than ±1 %, ±2 %, and ±4 %, respectively.

RF Receiver Specifications of Ubiquitous Network for Coexistence with Various Wireless Devices in 2.4GHz ISM-band

This paper describes the analysis for implementation of a radio frequency (RF) receiver for low-rate wireless personal area networks (LR-WPANs), namely IEEE 802.15.4, for coexistence with various wireless devices in 2.4 GHz ISM-band. With IEEE 802.15.4 standard specification, it provides analysis of receiver performance requirements containing the system noise figure (NF), system third-order intercept point (IIP3 ), local oscillator phase noise and selectivity. With some assumption, it illustrates the relationship between minimum detectable signal (MDS) and various situations considering for the effects of noise generated from other wireless devices according to communication distance. Here, we can infer the necessity of much tighter specification requirements than that of the standards for various communication field environments

Design of a CMOS Highly Linear Channel-Select Filter and Programmable Gain Amplifier for a WPAN Zero-IF Receiver

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier (PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance (Gm) cell. The PGA has a voltage gain varying from 0 to 65 dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85 dB THD and a 78 dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18 mum 1P6M n-well CMOS process. They consume 3.2 mW from a 1.8 V power supply and occupy an area of 0.19 mm 2