Seong-Jin Yeon

610 GHz InAlAs/In 0.75 GaAs Metamorphic HEMTs with an Ultra-Short 15-nm-Gate

Ultra-short-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) have been successfully fabricated with nano-gate fabrication technology and epitaxial optimization. We obtained an extrinsic maximum transconductance (Gm,max) of 1.65 S/mm and a current gain cutoff frequency (fT) of 610 GHz for 15-nm-gate HEMTs on GaAs substrates. Through a delay time analysis, the ultrahigh fT of this work is explained by an enhanced average electron velocity under the gate (Vave) of 4.3 x 107 cm/s, which was a result of reduction of gate length (Lg) and epitaxial engineering. This report is the first experimental demonstration of 15 nm InAlAs/TnGaAs metamorphic HEMTs (MHEMTs) with an extremely high fT of 610 GHz.

High-Speed Digital Circuits Using InP-based Resonant Tunneling Diode and High Electron Mobility Transistor Heterostructure

Resonant tunneling diodes (RTDs) exhibit a negative-differential-resistance (NDR) characteristic and a picosecond-level switching time (1.5 ps). The NDR characteristic provides the possibility of reducing circuit complexity and power consumption. The RTDs very fast switching characteristic provides the possibility of high-speed operation. Utilizing the RTDs characteristics, we designed and fabricated high-speed implementations of a static inverter, a three-stage ring oscillator, and basic Boolean logic gates. Using these results, we designed a 2-bit analog-to-digital converter (ADC) with reduced circuit complexity. Spice simulation proved that the designed ADC can operate at a sampling frequency of up to 10 GHz.

30 nm Triple-Gate In0.7GaAs HEMTs Fabricated by Damage-Free SiO2/SiNx Sidewall Process and BCB Planarization

A 30 nm In0.7GaAs high electron mobility transistor (HEMT) with triple-gate has been successfully fabricated using the SiO2/SiNx sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance (Rg), the etched-back BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width (Wg) of 2×100 µm. The fabricated 30 nm In0.7GaAs HEMTs showed Vth of -0.4 V, Gm,max of 1.7 S/mm, and fT of 421 GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50 nm InGaAs HEMTs if the initial line length can be reduced to below 50 nm order.

High-Speed and Low-Power Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology

A high-speed and low-power delayed flip-flop circuit with non-return-to-zero mode output using a new negative differential resistance logic element is proposed and fabricated using resonant tunneling diode (RTD)/high electron mobility transistor (HEMT) integration technology on an InP substrate. The number of devices used in the delayed flip-flop and the power dissipation has been significantly reduced by using the proposed scheme. The operation of the fabricated delayed flip-flop is demonstrated up to 26 Gb/s with a very low power dissipation of about 2.8 mW at a power supply voltage of 0.9 V.

High Electron Mobility Transistors Yield Improvement with Ultrasonically Assisted Recess for High-Speed Integrated Circuits

InAlAs/InGaAs high electron mobility transistors (HEMTs) have been a great contribution to the research and development of high-speed integrated circuits, owing to their high electron mobilities, high saturation velocities, and high sheet electron densities. In integrated circuits using a HEMT as active device, the gate recess process has considerable influence on the yield and uniformity. The wet recess of a 0.1 µm gate footprint has difficulty achieving a high yield greater than 98% due to a nonuniform reaction between the etchant and the semiconductor. A uniform initial reaction between the InGaAs cap layer and the wet etchant mainly determines the yield and uniformity. In this paper, we present an ultrasonically assisted recess method of promoting a uniform initial reaction in the recess process. This method enables us to achieve a high yield and a high uniformity in integrated circuits.

High-Speed and Low-Power Source-Coupled Field-Effect Transistor-Logic-Type Non-Return-to-Zero Delayed Flip-Flop Circuit Using Resonant Tunneling Diode/High Electron Mobility Transistor Integration Technology

We demonstrate a novel and compact implementation of high-speed and low-power source-coupled-field-effect transistor (FET)-logic (SCFL)-type non-return-to-zero (NRZ) delayed flip-flop circuit using resonant tunneling diode (RTD)/high electron mobility transistor (HEMT) integration technology on an InP substrate. The proposed circuit has several advantages of reduced device count, low power consumption, and reduced clock loading over previously reported circuits. The operations of the fabricated circuit was successfully confirmed up to 12.5 Gbits/s with a very low power consumption of about 11 mW.

Gate Length Reduction Technology for Pseudomorphic In0.52Al0.48As/In0.7Ga0.3As High Electron Mobility Transistors

Gate length reduction technology was developed for pseudomorphic high-electron-mobility transistors (P-HEMTs) applicable to nano-HEMTs. This technology utilizes various reactions between plasmas and dielectrics. Using optimum conditions for reducing gate length through pattern transfer in dielectric etching, we fabricated HEMTs having a sub-30 nm gate length reduced from the initial gate length of 0.13 µm. A HEMT with this technology has merits of both fine length definition beyond the limit of an electron beam (e-beam) lithography system and overcoming the metal filling problem caused by a high aspect ratio. The fabricated devices have high DC and RF performance characteristics, a transconductance of 1.35 S/mm, a maximum saturated current of 800 mA/mm and a cutoff frequency fT of 450 GHz.

Innovative Low damage Silicon Nitride Passivation of 100nm In0.45AlAs/In0.4GaAs Metamorphic HEMTs with Remote ICPCVD

In this paper, a novel low-damage silicon nitride passivation for 100 nm In0.45AlAs/In0.4GaAs MHEMTs has been developed using remote ICPCVD. The silicon nitride deposited by ICPCVD showed higher quality, higher density, and lower hydrogen concentration than those of silicon nitride deposited by PECVD. In particular, we successfully minimized the plasma damage by separating the silicon nitride deposition region remotely from ICP generation region, typically with distance of 34 cm. The silicon nitride passivation with remote ICPCVD has been successfully demonstrated on GaAs MHEMTs with minimized damage. The passivated devices showed considerable improvement in DC characteristics and also exhibited excellent RF characteristics (fT of 200 GHz).The devices with remote ICPCVD passivation of 50 nm silicon nitride exhibited 22 % improvement (535 mS/mm to 654 mS/mm) of a maximum extrinsic transconductance and 20 % improvement (551 mA/mm to 662 mA/mm) of a maximum saturation drain current compared to those of unpassivated ones, respectively. The results achieved in this work demonstrate that remote ICPCVD is a suitable candidate for the next-generation MHEMT passivation technique.

High Performance 50 nm InAlAs/In0.75GaAs Metamorphic High Electron Mobility Transistors with Si3N4 Passivation on Thin InGaAs Layer

We fabricated 50 nm InAlAs/InGaAs metamorphic high electron mobility transistors (HEMTs) with a very thin barrier. Through the reduction of the gate–channel distance (dGC) in the epitaxial structure, a channel aspect ratio (ARC) of over three was achieved when Lg was 50 nm. We inserted a thin InGaAs layer as a protective layer, and tested various gate structures to reduce surface problems induced by barrier shrinkage and to optimize the device characteristics. Through the optimization of the gate structure with the thin InGaAs layer, the fabricated 50 nm metamorphic HEMT exhibited high DC and RF characteristics, Gm of 1.5 S/mm, and fT of 490 GHz.

Novel sloped etch process for 15nm InAlAs/InGaAs metamorphic HEMTs

We developed a new technology that reduces gate length with modified sloped etch process to fabricate nanometer scale high-electron mobility transistors (HEMTs). The polymer deposition and Si3N4 etching with positive slope make this technology realizable. A HEMT with this technology has merits of both fine length definition beyond the limit of an electron beam (E-beam) lithography system and overcoming the metal filling problem caused by a high aspect ratio. Using this technology, we could get 15 nm gate length from initial 40 nm line pattern. The fabricated 15 nm InAlAs/InGaAs metamorphic HEMTs (MHEMTs) have high DC and RF performance characteristics, a transconductance of 1.6 S/mm, a cutoff frequency fT of 580 GHz.