Seongbo Shim

Parallel machine scheduling considering a job-splitting property

This paper focuses on the problem of scheduling jobs on parallel machines considering a job-splitting property. In this problem, it is assumed that a job can be split into a discrete number of subjobs and they are processed on parallel machines independently. A two-phase heuristic algorithm is suggested for the problem with the objective of minimizing total tardiness. In the first phase, an initial sequence is constructed by an existing heuristic method for the parallel-machine scheduling problem. In the second phase, each job is split into subjobs considering possible results of the split, and then jobs and subjobs are rescheduled on the machines using a certain method. To evaluate performance of the suggested algorithm, computational experiments are performed on randomly generated test problems. Results of the experiments show that the suggested algorithm performs better than an existing one.

Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement Optimization

In directed self-assembly lithography (DSAL), an inter-cell cluster of contacts, which crosses the boundary of cells, is more likely to cause patterning failure because corresponding guide pattern (GP) has not been verified beforehand. All forms of inter-cell clusters can systematically be identified and grouped, which allows us to define DSA defect probability when two arbitrary cells are placed side by side. We then address post-placement optimization, in which some cells are flipped and some cells are swapped with their adjacent cells so that the number of whitespaces inserted in between cell pairs of high defect probability is minimized. Experiments with a few test circuits demonstrate 11% increase of placement density, on average, with no expected DSA defects.

Redundant via insertion for multiple-patterning directed-self-assembly lithography

In sub-7nm technology, the size and pitch of vias are much smaller than optical resolution limit, and directed self-assembly lithography with multiple patterning technology (MP-DSAL) has been proposed as a solution. In MP-DSAL, vias that are close are clustered and patterned together via DSAL process, and via clusters that are close are printed using different masks via MP. Redundant vias, which are typically used for better via manufacturability, should be inserted very carefully in MP-DSAL because some redundant vias may cause large and complex via clusters, which are undesirable in DSAL; some other redundant vias may cause mask assignment of via clusters impossible, often called MP coloring conflict. Redundant via insertion for MP-DSAL is addressed. The goal is to insert maximum number of redundant vias while all via clusters are manufacturable and MP coloring conflicts do not occur. The problem can be solved through ILP, which we show; a practical heuristic algorithm is also proposed. The definition of manufacturable clusters is important; defect probability is introduced for this purpose. Experiments in 7-nm technology indicate that 9.8% vias, on average of test circuits, do not receive redundant vias after heuristic algorithm is applied, while that number becomes 21.2% in simple intuitive method; in ILP run on very small circuits, redundant vias are not inserted in 9.1% of vias, which is comparable to the result of heuristic.

The new test pattern selection method for OPC model calibration, based on the process of clustering in a hybrid space

Model-based Optical Proximity Correction (OPC) is widely used in advanced lithography processes. The OPC model contains an empirical part, which is calibrated by fitting the model with data from test patterns. Therefore, the success of the OPC model strongly relies on a test pattern sampling method. This paper presents a new automatic sampling method for OPC model calibration, using centroid-based clustering in a hybrid space: the direct sum of geometrical sensitivity space and image parameter space. This approach is applied to an example system in order to investigate the minimum size of a sampling set, so that the resulting calibrated model has the error comparable to that of the model built with a larger sampling set. The proposed sampling algorithm is verified for the case of a contact layer of the most recent logic device. Particularly, test patterns with both 1D and 2D geometries are automatically sampled from the layer and then measured at the wafer level. The subsequent model built using this set of test patterns provides high prediction accuracy.

The effective etch process proximity correction methodology for improving on chip CD variation in 20 nm node DRAM gate

This paper presents an effective methodology for etch PPC (Process Proximity Correction) of 20 nm node DRAM (Dynamic Random Access Memory) gate transistor. As devices shrinks, OCV(On chip CD Variation) control become more important to meet the performance goal for high speed in DRAM. The main factors which influence OCV are mask, photo, etch PPE (Process proximity effect) in DRAM gate. Model based etch PPC is required to properly correct Etch PPE as device density increases. To improve OCV in DRAM gate, we applied new type of etch loading kernel. It is called Vkernel which accounts for directional weight from the point of interest. And we optimized the etch PPC convergence by optimizing the etch PPC iteration. Because of density difference between spider mask and real gate mask, the skew difference occurs between them. We tested the effect of long range density using same real gate pattern clip by varying mask open image size from 0.5 ~ 10 mm. The ADI CD difference was on average in the order on 2 nm for varying mask open image size. But the ACI CD difference (the average of CD range by varying open image size) was very noticeable (about 15 nm). This result shows that etch skew affected by long range density by mm unit size. Due to asymmetrical pattern in real gate mask, spider mask which have symmetrical patterns is necessarily used to make PPC model. The etch skew of real pattern clip in spider mask was not also the same for the real pattern in real gate mask. To reduce this skew difference between spider mask and real mask, we applied open field mask correction term and long range density effects correlation equation to PPC modeling. There was noticeable improvement in the accuracy of PPC model. By applying these improvement items, OCV of 20 nm node DRAM gate is shown to improve up to 67%.

Synthesis of lithography test patterns through topology-oriented pattern extraction and classification

Comprehensive and compact test patterns are crucial to the development of new semiconductor technology. In particular, the random nature of routing layers tends to create many hotspots, corresponding to patterns which are difficult to predict. Conventional group of test patterns consists of parametric typical patterns and real layout clips, which contain a lot of redundancy. The paper addresses a problem of generating comprehensive yet compact group of test patterns for random routing layers. A new method of pattern extraction and classification is proposed to solve the problem.

Mask optimization for directed self-assembly lithography: Inverse DSA and inverse lithography

In directed self-assembly lithography (DSAL), a mask contains the images of guide patterns (GPs), which are patterned on a wafer through optical lithography; the wafer then goes through DSA process to pattern contacts. Mask design for DSAL, which is the opposite of the above processes, consists of two key steps, inverse DSA and inverse lithography, which we address in this paper. In inverse DSA, we progressively refine GPs until they produce target contacts as closely as possible. GP is defined as a function of a few geometry parameters, and how sensitive the contacts are to the parameters are calculated which then guides how much the GP should be refined. In inverse lithography, mask is progressively refined so that target GPs are produced. Mask is defined by pixel values and their gradient guides the direction that the mask should be refined. There are too many pixels for gradient calculation; the method to approximate calculation is proposed. Inverse DSA and inverse lithography are extended to handle process variations. We modify basic inverse lithography so that the resulting mask becomes less sensitive to lithography variations; basic inverse DSA is modified so that it provides the way this sensitivity can be checked.

Etch proximity correction through machine-learning-driven etch bias model

Accurate prediction of etch bias has become more important as technology node shrinks. A simulation is not feasible solution in full chip level due to excessive runtime, so etch proximity correction (EPC) often relies on empirically obtained rules or models. However, simple rules alone cannot accurately correct various pattern shapes, and a few empirical parameters in model-based EPC is still not enough to achieve satisfactory OCV. We propose a new approach of etch bias modeling through machine learning (ML) technique. A segment of interest (and its surroundings) are characterized by some geometric and optical parameters, which are received by an artificial neural network (ANN), which then outputs predicted etch bias of the segment. The ANN is used as our etch bias model for new EPC, which we propose in this paper. The new etch bias model and EPC are implemented in commercial OPC tool and demonstrated using 20nm technology DRAM gate layer.

Physical simulation for verification and OPC on full chip level

In this paper, we introduce a rigorous OPC technology that links the physical lithography simulation with the OPC. Firstly, the various aspects of the rigorous OPC, related to process flow, are discussed and the practical feasibility of the embedded rigorous verification is taken into account, which can make the rigorous treatment of the full-chip level possible without any additional manual efforts. We explain an embedded rigorous verification flow and the basic structure of its functionality. Finally, its practical application to real cases is discussed.

Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography

Guide-patterns (GPs) are critical to the construction of contacts and vias in directed self-assembly (DSA) lithography. Simulations can be used to verify GPs, but runtime is excessive. Instead, we categorize the shapes of GPs using a small number of geometric parameters. Then a verification function is built to predict whether a GP will produce the required contacts, as follows: a vector in parameter space is constructed to represent each GP in a test set; the acceptability of each GP is then assessed by DSA simulation, and each vector is tagged “good” or “bad” accordingly; next, the parameter space is deformed to convert a radial distribution into one in which the good and bad vectors can be separated by a hyper-plane, which finally becomes the verification function. We also show how to reduce the dimensionality of the parameter space by principal component analysis, and how to generalize the geometric description of GPs to allow different types of GP to be verified in a uniform fashion. The proposed GP verification is demonstrated in 10 nm technology.